Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (86239)	7/27/1999 10:43:00 PM
From: kapkan4u	Read Replies (1) \| Respond to of 186894

<You can see that the main bottleneck becomes the memory channel. If there is only one PC100 SDRAM channel in the system, then the bandwidth between memory and chipset is 0.8 GB/sec. The bandwidth between processor and chipset is 1.6 GB/sec, which is overkill in regard to the memory bandwidth. On the other hand, if DRDRAM were used, then the bandwidth between memory and chipset becomes 1.6 GB/sec, which then makes the extra bandwidth between processor and chipset much more useful.> What is the combined bandwidth of PCI and AGP interfaces? If it is close to 0.8 GB/sec then there is no vacant bandwidth. Right? What about DDR266 SDRAM instead of DRDRAM? Kap.

To: Tenchusatsu who wrote (86239)	7/28/1999 1:00:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 186894

Ten, Think of the chipset as the crossroads between four interfaces: the processor bus, the memory, AGP, and PCI. Let's not forget IDE! Scumbria

To: Tenchusatsu who wrote (86239)	7/28/1999 1:15:00 PM
From: Ali Chen	Read Replies (2) \| Respond to of 186894

Ten, <You can see that the main bottleneck becomes the memory channel.> No you can't. If your theories are true, application performance would be INDEPENDENT from the CPU core speed. In contrast, brief examination of the Intel performance briefs shows us, e.g.: developer.intel.com P-III, frequency change (relative to 450): 450 1.0 500 1.11 550 1.22 3-D Winbench light&transform: 57.5 1.0 63.9 1.11 68.8 1.19 developer.intel.com Sysmark98 - system performance: 192 1.00 210 1.09 224 1.17 As you may see, the 22% increase in core frequency still gives you a 19% gain in SSE-transformations and 17% return in business applications. One can conclude that even on most demanding business apps (as per BAPCO suit) the memory accounts for no more than 25% of the runtime, and therefore is not exactly the "bottleneck" yet. <If there is only one PC100 SDRAM channel in the system, then the bandwidth between memory and chipset is 0.8 GB/sec. The bandwidth between processor [Athlon] and chipset is 1.6 GB/sec, which is overkill in regard to the memory bandwidth.> Maybe this is why this "ridiculous" Athlon lags in performance behind P-III/Xeon? Or it isn't? :) :)