Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (27399)	8/22/1999 10:19:00 PM
From: wily	Read Replies (1) \| Respond to of 93625

Dan3, Tell me what you think would be the penetration of Rambus in the PC market one year from now if the price premium was 10%. Thanks, wily

To: Dan3 who wrote (27399)	8/22/1999 10:25:00 PM
From: Jdaasoc	Read Replies (1) \| Respond to of 93625

Dan3: <<rambus has more stringent location requirements for the memory traces>> ... and your wrong again. What else is new. More stringent than what? Any technology that moves data at 800 MHz per pin will have to be stringently designed than the only memory you can compare it to, PC100. Don't waste you time posting unless you can add something to the topic at hand.

To: Dan3 who wrote (27399)	8/23/1999 5:04:00 AM
From: unclewest	Read Replies (1) \| Respond to of 93625

A lower pin count is desirable because it lowers costs. If rambus equipped PCs start coming in cheaper than otherwise equivalent SDRAM PCs, great. But right now, I don't think anyone is expecting that. Quite the opposite, in fact. A lower pin count has no intrinsic value. dan, please read the first and last sentences of your statement above...kinda funny isn't it? when you responded to my post did you realize that was dell talking not me? i noticed you skipped over this part of my quote from dell. unclewest n comparison, an additional SDRAM interface requires 32 pins. Although an additional 132-pin interface may be a reasonable approach for expanding server memory, it is not appropriate for workstations or desktop PCs due to the component cost and system board space required. Moreover, increasing the clock rate or widening the data path beyond PC 133 parameters for a single SDRAM channel will increase the difficulty of controlling emissions, maintaining signal integrity, and meeting timing margins.

To: Dan3 who wrote (27399)	8/23/1999 5:07:00 AM
From: John Walliker	Read Replies (1) \| Respond to of 93625

Dan3, A lower pin count has no intrinsic value. While the lower pin count makes laying out the motherboard easier, and provides a benefit if it allows better component placement, rambus has more stringent location requirements for the memory traces, so even that may end up no better than a wash. If a large pincount is used space has to be found round the edges of the die for the bonding pads. This then limits the smallest die size that can be achieved, regardless of reduced feature size. If a large pincount is used, ground-bounce becomes an increasing problem which can only be overcome by adding yet more ground pins or by slowing the rate of change of drive current (which slows the interface down) or using differential signalling (which adds yet more pins). (Groundbounce is the phenomenon where many simultaneously switching outputs cause a large transient current to flow through the ground pins of the package. Their inductance causes a transient voltage change which can disturb the detection of other signals or the internal operation of the device. If the data streaming ability of rambus ever looks like it's of any use in a PC, we'll return to interlaced memory, the way all of the old 486s were before cache became universal and streaming data was determined to not be worth the $10 a couple of extra memory sockets added to the cost of a motherboard. But this will require using a second memory controller because the settling time of the bus is already a large part of the available time between memory accesses. In the days of the 486 memory access times were around 80ns, leaving lots of time to interleave memory banks onto one bus. Even if it were possible it would also increase the granularity problem. John