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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (70329)	8/30/1999 6:45:00 PM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 1573697

Re <The massive numbers of K6-3s flooding the market give us a hint as to AMD's inability to manufacture large caches & large die. The Athlon would need 512K on die L2 to make a difference and AMD has real problems manufacturing the K6-3 with 256K. The L2 doesn't care what the architecture is, it cares what the defect density is.> Your point is well taken. However, remember this. If the K62/K63 designs originated from NexGen, they were designed for an IBM process that included a local interconnect level. This local interconnect level allows a 12% - 15% advantage in SRAM cell size and a somewhat smaller advantage in logic density. However, it comes at a price. It is a difficult level from a processing point of view and, if not done correctly, a source of significant yield loss. My understanding is that AMD eliminated this level in the K7 design, opting for the more conventional easier approach. If so, this is probably a smart move on their part and may enable them to yield large L2 caches much more easily. Can anyone familiar with the history of K62/K63 confirm the local interconnect as being the main yield detractor and whether or not AMD did, in fact, abandon it in the K7 design? I asked this question in an earlier post and got ZERO response. THE WATSONYOUTH

To: Elmer who wrote (70329)	8/30/1999 8:05:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1573697

Elmer, The massive numbers of K6-3s flooding the market give us a hint as to AMD's inability to manufacture large caches & large die. K7 has the largest L1 in the x86 world, and runs faster than any other x86 CPU. Please stop the FUD. Scumbria

To: Elmer who wrote (70329)	8/31/1999 2:35:00 AM
From: Petz	Read Replies (2) \| Respond to of 1573697

Elmer, re:<The massive numbers of K6-3s flooding the market give us a hint as to AMD's inability to manufacture large caches & large die> IMO, AMD doesn't need to get any better performance clock-for-clock to compete with the sixth generation CuMine. So, I hope their first 0.18µ Athlon has 512K of integrated half speed cache. The first chips coming out at 0.18 should run at 850 or 900 MHz. Higher end chips could have DDR SRAM L2 (same latency as half-speed L2 with double the throughput). 1/1.5 speed L2 is also apparently a possibility. The flexibility of the Athlon core w.r.t. L2 rate is a definite plus that could possibly even be used to decide on L2 speed at test time, and mark the chips accordingly. Petz