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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (70702)	9/2/1999 3:04:00 AM
From: Process Boy	Read Replies (1) \| Respond to of 1574055

Paul - <TWY - Re: " The PPCs Motorola delivered to Apple for their G4s appear to be from a .25um technology and NOT .18um as they previously advertized. It's a 1.8V process (10.5 million devices) at 83mm2. The G3 predecessor from IBM was 40mm2 (6.5 million devices) in .25um technology. Adding AtliVec instructions approximatalLy doubled the size of the chip. So this is not a .18um process.(at least not in the BEOL) If not, then AMD will be scheduled to produce .18um Cu BEOL processors before their mentor Motorola does it." NOT according to THIS article: "Motorola said the chip is being fabricated with a new 0.18-micron (0.15-micron L-effective) copper HiPerMOS process. All six levels of metal use copper instead of traditional aluminum interconnects. "> I believe what WY is suggesting the the Front End of the process is .18", but the G4 die size vs. circuit density doesn't match up for a true .18 back end. I.e., maybe MOT's Cu process is not ready for .18 design rules. I don't know, but I find that an interesting set of circumstances if true. I believe AMD's front end Athlon process may well be a .18 type process, but of course it would still have .25 interconnects. If MOT is behind in delivering their own .18 Cu, then I wonder how Dresden is doing? Again, this is a lot of ifs, and I'm only speculating out loud. I wish I knew more about the Gx processors to try and validate WY's postulations, but I don't. PB

To: Paul Engel who wrote (70702)	9/2/1999 3:47:00 AM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 1574055

Re. <Motorola said the chip is being fabricated with a new 0.18-micron (0.15-micron L-effective) copper HiPerMOS process. All six levels of metal use copper instead of traditional aluminum interconnects. > Well, it sure does say that (.18um). But the numbers just don't add up for me. How could the G4 double in size over G3 (83mm2 vs. 40mm2) by adding AltiVec while at the SAME time going from .25um groundrules to .18um groundrules. That would mean the AltiVec addition would have to be much bigger than the entire original G3. I doubt it. Also, .15um Leff in .18um groundrules?? Intel is doing better than that in .25um groundrules. And, only 450MHz now in .18um? That's pathetic. Maybe they mean (.18um Ldrawn / .15um Leffective) for the gate level only and the groundrule generation is actually .25um. Then, at least, the numbers make some sense. If I'm wrong on this, I'll admit it on the thread but I am not ready to concede anything yet. THE WATSONYOUTH