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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Alan Bell who wrote (28858)	9/7/1999 2:15:00 AM
From: Bilow	Read Replies (2) \| Respond to of 93625

Hi Alan Bell; Thanks for the response. I am not predicting that Dell will not be able to build a rambus machine. I never predicted that Samsung would be unable to build a rambus chip, for that matter, just that it is a lot more trouble than SDRAM or DDR. My guess is that Dell will begin shipping rambus based machines soon, as announced. My only note is that this whole direct rambus for high end computers kick has had a lot of unpredicted delays in the past, so investors should not be surprised by delays in the future. Rambus seems to be priced for perfection, taking a look at the royalty numbers, and making conservative estimates of percentage shipments. I have no doubt that the big players will have the advantage on building rambus boards. I don't think that the little board houses and small companies are going to concentrate on rambus, but they won't have to. Imagine having to do a rambus desing using Orcad, for instance, I doubt they'll try it. It is obvious to me that a lot of the second tier usages of DRAM will go to SDRAM or DDR because of the complicated interface requirements of RDRAM. I think that is probably what the Astrophysicist quoted on this thread recently was on to. (The one that Dan3 defended just a little too strongly IMHO). The basic problem with rambus is the higher cost of manufacturing without significantly higher performance. The second basic (temporary) problem is that of the risk of availability. That the technology is difficult just increases risk, as we all agree; rambus runs a lot closer to the edge. But that running close to the edge is not accompanied by significant performance improvements. Regarding the rambus adjustment of Vref. I am unaware of the details of that, please inform. DDR SDRAM also uses a Vref, and that Vref is also defined by the controller, but it is primarily there to avoid problems with ground bounce, I thought. By the way, SSTL_2 uses much higher voltage swings, so it doesn't need to mess around with feedback on Vref. Incidentally, a cool schmoo plot that I located while looking for DDR specifications. You sound like you would appreciate this sort of thing: (pdf, page 19) sscs.org If you go back and read the rambus note on board layout, I believe that you will find that some of their packages do require vias. This would also depend on the package that the controller was in. A recent design I've seen with a big (560-pin) FBGA (from Xilinx) had a via under each pin (yech!), and this made the routing about as ugly as I've seen. It also ran the layer count way up, increasing the board cost. If the engineer who was responsible wasn't just about the highest regard guy in this area, I would have thought it was a design mistake. I will ask more about it the next time I run into him. In any case, requiring that your memory interface not have vias isn't going to make your layout guy like you any extra. What I am predicting is that AMD is going to pick up a lot of market share at the high end, due to increased costs to those using INTC CPUs. I think that this will be a very serious problem for INTC by 3Q00, and that they may reconsider their lack of support for DDR between now and then. If problems with availability of rambus parts continues, and INTC continued to stonewall DDR, they might have to wake up to DELL making a deal with AMD. A lot is riding on INTC's decision, and the decision they can make to avoid a possibilty of a lot of really nasty design losses is to announce support for DDR. I think that would likely be negative for RMBS's stock price. -- Carl