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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (29136)	9/10/1999 9:51:00 AM
From: grok	Read Replies (1) \| Respond to of 93625

RE: <The Samsung white paper that concludes RDRAM has slightly less latency than PC100 SDRAM is a joke, due to a calculation error, at least as far as PC memories are concerned.> No, Carl, it's not a calculation error. It is a deliberate misrepresentation intended to mislead.

To: Bilow who wrote (29136)	9/10/1999 10:32:00 AM
From: John Walliker	Respond to of 93625

Carl, Which reminds me. Regarding the VOLxIOL power, you say Not very much power. But your calculation for VOL x IOL is wrong by a couple orders of magnitude. The figure you quote, 0.3v X 1mA is so small that the engineers would never have put it on a data sheet, as it is not worth worrying about. I will let you correct your own calculation. Not my calculation. I quoted directly from the Samsung data sheet KM416RD8AC(D)/KM418RD8AC(D) revision 1.0 July 1999 filename rdram128dAbook.pdf, page 49, table 20 where VOL,CMOS is characterised at IOL,CMOS of 1mA. I did not attach any special significance to this characteristic, you did. However, the symbols have been used in different ways in the two parts of the data sheet, so this is something of a red herring. The thing to notice is that this current is the least that the RDRAM can consume, and still be available for a minimum latency access. When a data sheet says maximum current, I assume that it means maximum under all temperature and voltage and process conditions and not minimum. Funny, my KM416RD8C/KM418RD8C data sheet from Samsung, downloaded today, gives 120mA max. There are several types of RDRAM, I chose the version that got INTC's okay. There are also two specifications, one for 600MBps and the other for 800MBps speeds. My guess is that you chose the 600MBps current numbers by mistake, as my data sheet lists 100mA for the standby current at 600MBps. Not that much difference. I have now downloaded datasheet KM416RD8C(KM418RD8C).pdf which is revision 0.9, April 1999 and I see where your numbers are coming from - an old data sheet. See developer.intel.com to see that the "A" version of the device which I was referring to has indeed been qualified by Intel. Its just that Samsung have forgotten to mention this on their web site. I will look more closely at your power calculations, using the more recent data and comment later. John

To: Bilow who wrote (29136)	9/10/1999 12:16:00 PM
From: kash johal	Read Replies (2) \| Respond to of 93625

Carl, Re:"power analysis" Thanks for the power analysis - you make a compelling case IMHO. Having said that it is no surprise that RDRAM takes much more power due to termination and loads etc. However the key is performance. Despite the debacle of Dells senior engineer publishing those insane charts at IDF I still expect DRDRAM to be superior in some benchmarks. And i expect Intel to use that heaviliy in marketing. So i expect the stock to ramp short term. Longer term I am unsure on Rambus. it could be a huge bust- if apps to drive memory bandwith don't become mainstream. Just my 2cents, regards, Kash

To: Bilow who wrote (29136)	9/10/1999 10:41:00 PM
From: Dan3	Read Replies (2) \| Respond to of 93625

Re: Re current consumption. Conclusion: RDRAM uses more power... A really interesting post, clearly explaining some difficult concepts. Have you considered teaching? I've taught a few classes at two local colleges, and it can be very rewarding. Or maybe you already are teaching - your posts show signs of such experience. If you aren't, I can tell you that adjunct pay is nominal, but the experience can be very satisfying. You would do a terrific job and I think that you'd enjoy it a great deal. There is a terrible shortage of good instructors in technical fields. If you aren't already, you should consider it, your talents are probably largely going to waste on this thread. Some students just won't listen. Dan

To: Bilow who wrote (29136)	9/11/1999 10:38:00 AM
From: John Walliker	Read Replies (6) \| Respond to of 93625

Carl, Some more thoughts about your post. Rather than comparing systems with three DDR RAMS in parallel lets get realistic and use four 16-bit DDR RAMS of the type you suggested from IBM (IBM0625164). A minimum system using these devices would have a total capacity of 128 Mbyte and a data transfer rate of 1.6 Gbyte/s at 100 MHz or 2.1 Gbyte/s at 133 MHz. There is no immediate prospect of 143 MHz chipset support, so lets forget about the 7ns cycle time you used. Comparisons are easier if the same peak data transfer rate is used, so lets work at 100MHz. We are assuming a hard-working system, so all four banks of the IBM device would be active. For burst accesses the supply current will be about 100mA. This number comes from the -12 part, where the minimum cycle time is 8ns. Therefore, the total RAM supply current (not including bus drive) will be about 400mA @2.5V To achieve the same memory capacity with DRDRAM will require eight chips, of which one will typically be active and the others in standby or sleep mode. The active chip will take 490mA max read current or 575mA max write current. Say 507 mA average for a 4:1 read/write ratio. If all the other chips are in NAP mode, drawing 4mA each then the total current (excluding bus drive) will be 507 + 74 = 535mA. If all the other chips are in STBY mode, then the total current will be (excluding bus drive) will be 507 + 7105 = 1242mA. This is a worst case figure. The real power consumption will probably be somewhere in between, so lets assume half the chips are in NAP mode, the rest in STBY or ATTN (active). Then the Rambus supply current (excluding bus drive) will be 507 + 44 + 3105 = 838 mA. OK. This is just over twice as much as the IBM 256 Mbit chips, but not the factor of 3.7 or 6.6 you claim. Your assumption is that the factor of 6.6 applies to portable systems where as many of the chips are inactive as possible, but according to my analysis the relevant ratio would be 535/400 = 1.34. Also remember that we are comparing IBM 256Mbit DDR chips with Samsung 128Mbit chips. Samsung have announced that they will be shipping 256 Mbit devices within the next few months. These will undoubtedly push the equation more in favour of Rambus. Now lets look at the power consumption of the bus. The IBM DDR chips use SSTL2 signalling where the static drive current from each pin is about 15mA. There are 42 signal pins per chip, but many of them only need to be driven once per four chips. Only the data lines will be independent. Therefore 164 + 42-16 = 90 individual pins are likely to be driven at once. Therefore 9015=1350mA system supply current is needed to drive the bus. This value will be significantly higher under dynamic conditions. For Rambus, there are 28 pins carrying Rambus signalling level. All the others are CMOS and can be ignored. The drive current on each pin is about 30 mA for logic 1 and zero for logic 0. Therefore average current is about the same as for SSTL2 at 15mA per pin. Therefore, total average current used for Rambus signalling is about 15*28=420mA. Adding chip and bus supply currents up gives the following: DDR using four IBM 256k bit chips 400 + 1350 = 1750 mA Rambus using eight Samsung 128k bit chips 838 + 420 = 1258 mA (half of chips in NAP mode). Therefore, the system power consumption using Rambus is about 1.4 times LOWER than DDR even though the Rambus chips used in this example are of an older generation than the DDR ones. John