Hi John Walliker; Looks like its up to me to critique your current requirement
calculation...
I'll put your post in italics, with my comments in regular and bold.
Rather than comparing systems with three DDR RAMS in parallel lets
get realistic and use four 16-bit DDR RAMS of the type you suggested from IBM
(IBM0625164).
Okay. I know that computing bandwidth per watt is a little beyond the capability
of most of the readers of this thread. This will simplify things, and it really
doesn't effect power consumption much.
A minimum system using these devices would have a total capacity of 128 Mbyte
and a data transfer rate of 1.6 Gbyte/s at 100 MHz or 2.1 Gbyte/s at 133 MHz.
There is no immediate prospect of 143 MHz chipset support, so lets forget about
the 7ns cycle time you used.
I think that if you look around, you will find support for 7ns cycle times,
but I don't think that this is a serious cause for error.
Comparisons are easier if the same peak data transfer rate is used, so lets work
at 100MHz.
Agreed.
We are assuming a hard-working system, so all four banks of the IBM device
would be active. For burst accesses the supply current will be about 100mA.
This number comes from the -12 part, where the minimum cycle time is 8ns.
This is a minor error. The 100mA spec is for a -12 part cycled at 8ns. We
are agreed to analyze a 10ns cycle time. There is a note that applies. One
of the things that working engineers eventually learn is to never, never, never
ignore the notes on data sheets. Note 1 reads:
These parameters depend on the cycle rate and are measured with the cycle
determined by the minimum value of tCK and tRC.
Since current draw in CMOS parts scales as frequency, increasing the period from
8ns to 10ns has the effect of reducing current requirements from 100mA to about
80mA.
Therefore, the total RAM supply current (not including bus drive) will be
about 400mA @2.5V
about 320mA @2.5V, per the previous note.
To achieve the same memory capacity with DRDRAM will require eight chips,
of which one will typically be active and the others in standby or sleep mode.
If we agree to have RDRAMs in sleep mode, we also have to agree to having
nasty latency periods. Latency is probably as important as bandwidth, so
it is unlikely that the system designers are going to nap parts. I think this
assumption is contrary to the assumption that this was a hard working system.
The active chip will take 490mA max read current or 575mA max write current.
Say 507 mA average for a 4:1 read/write ratio.
Agreed.
If all the other chips are in NAP mode, drawing 4mA each then the total current
(excluding bus drive) will be 507 + 7*4 = 535mA.
Unrealistic.
If all the other chips are in STBY mode, then the total current will be (excluding
bus drive) will be 507 + 7*105 = 1242mA. This is a worst case figure. The real
power consumption will probably be somewhere in between, so lets assume half
the chips are in NAP mode, the rest in STBY or ATTN (active).
Unrealistic.
Then the Rambus supply current (excluding bus drive) will be
507 + 4*4 + 3*105 = 838 mA.
1242mA.
OK. This is just over twice as much as the IBM 256 Mbit chips, but not the
factor of 3.7 or 6.6 you claim.
1242ma / 320ma = 3.9
Your assumption is that the factor of 6.6 applies to portable systems where as many
of the chips are inactive as possible, but according to my analysis the relevant
ratio would be 535/400 = 1.34.
You are assuming here that in a portable system, that the system is always being
hard worked. Actually, portable systems, like desktop sytems, spend most of their
time spinning their wheels. In this case, the 6.6 current ratio applies. I doubt
that even 1% of the time a portable is on it is under hard use.
Also remember that we are comparing IBM 256Mbit DDR chips with Samsung 128Mbit chips.
Samsung have announced that they will be shipping 256 Mbit devices within the next
few months. These will undoubtedly push the equation more in favour of Rambus.
The fact is that 256Mb DDRs are available now. 256Mb RDRAMs are in the future.
By the time 256Mb RDRAMs are available, who knows what size DDRs will be available.
This is just a matter of availability.
Now lets look at the power consumption of the bus.
The IBM DDR chips use SSTL2 signalling where the static drive current from each pin is
about 15mA.
The 15mA you are quoting is the Output Minimum Source(Sink) DC Current.
The actual currents in a particular part are going to be a lot higher.
See the note I posted before this one for the SSTL_2 specification.
There are 42 signal pins per chip, but many of them only need to be driven once per
four chips. Only the data lines will be independent. Therefore 16*4 + 42-16 = 90
individual pins are likely to be driven at once. Therefore 90*15=1350mA system supply
current is needed to drive the bus. This value will be significantly higher under
dynamic conditions.
While there are 42 pins, some of them aren't toggling. In particular, /CS, CKE, UDM,
and LDM will have logic values of 0,1,0, and 0, respectively, essentially always.
(Though UDM and LDM might be used once in a while if the memory allows unaligned or
single byte writes.) This leaves 38 pins, of which 16 carry double rate data, and
18 carry at most single rate data, and the remaining four are 100MHz clocks.
For the system, the designer might or might not drive the UDM, LDM and WE lines
separately, depending on whether unaligned or single byte writes are accepted.
Assuming unaligned, there are 15 control lines with 5 pins, and 12 control lines
with 2 pins, each carrying information at a 100MHz rate.
There are a total of 64 data lines at double data rates, each with two pins.
Of the four clock pins, four would typically be shared, while the other two are
specific to the chip. That gives a total of 8 two-pin 100MHz clocks, and 2 five-pin
100MHz clocks.
The clocks change at 100Mhz. The data changes at most at 100MHz, but assuming
that half the data follows data of the same type, the average rate frequency
will be 50MHz. The (active) control lines change at most at 50MHz, but under
the same assumption, the average frequency will be 25MHz. Now we can compute
current, given figures for the capacitance and voltage swing. Of course the
100MHz clocks cycle at 100MHz.
The supply voltage is 2.5volts, but SSTL_2 only swings 1.5 volts (see IBM's spec
SSTL_2 Output Buffer Characteristics, vOL, vOH, page 47), so the amount of charge
being moved on the capcitors is Q = 1.5xC, where C is the capacitance. The current
is then I = 1.5xCxF, where F is the frequency.
Assuming 2pF of board trace capacitance per pin, and assuming all the controller
chips pins are 4pF, and using IBMs worst case specs for pin capacitance, we get
the following table:
Pin Tot Per Pin Pin
Type Freq. x Cap. = Current x Quantity = Total
---- ------ ------ ------- -------- -----
Data 50MHz 14.5pF 0.63mA 64 40.0mA
Ax 25 30.0 0.75 17 12.8 (Includes BAx, /xAS)
xDM 25 14.5 0.36 8 2.9
WEx 25 12.0 0.30 8 2.4
DQCK 100 14.5 1.45 8 11.6
CLK 100 30.0 3.00 2 6.0
other 1 30.0 0.03 2 0.1 (CKE and /CS)
------
Grand total: 75.8mA
I admit that I haven't included the capacitance of the termination on
the address lines, and these numbers look low to me, but at most by a factor
of two or so. Your figures are 18 times larger.
For Rambus, there are 28 pins carrying Rambus signalling level. All the others are CMOS
and can be ignored. The drive current on each pin is about 30 mA for logic 1
and zero for logic 0. Therefore average current is about the same as for SSTL2 at 15mA
per pin.
The 30mA spec for rambus iOL is the minimum value. It can actually go up
as high as 90mA. This would increase your numbers by a factor of three. So what
to choose for the impedance of the channel? How's about the impedance that is
required in order to use RIMMs? This is 28ohms. So the required current is
easy to compute, given a voltage drop of from 1.8 to 0.9 volts.
The data lines are doubly terminated. I assume that the others are singly
terminated. If they are also doubly terminated, (which would improve the
characteristics of the line somewhat), the currents on them would be doubled.
Type E / R = I # Current
------ --------------- -- -------
Single 0.9 / 28 = 32mA x 12 = 384mA
Double 0.9 / 14 = 64 x 16 = 1024
------
Total: 1408mA
Average 704mA
Note that the 64mA that I am using is right in the middle of the RDRAM
specification of 30 to 90mA. It is undoubtedly the correct value.
Therefore, total average current used for Rambus signalling is about 15*28=420mA.
704mA.
Adding chip and bus supply currents up gives the following:
DDR using four IBM 256k bit chips 400 + 1350 = 1750 mA
Wrong by a factor of six: 320 + 76 = 386mA
Rambus using eight Samsung 128k bit chips 838 + 420 = 1258 mA (half of chips in NAP mode).
1242 + 708 = 1950 mA (Using correct current and no chips in NAP mode).
Therefore, the system power consumption using Rambus is about 1.4 times LOWER than DDR
even though the Rambus chips used in this example are of an older generation than the
DDR ones.
Correct current ratio is around 5.
You know, you can screw around with my calculations quite a lot and still
come to the conclusion that RDRAM is a power hog. Assume a higher board
capacitance. Use 2.5 volts instead of 1.5 volts for the switched voltage.
Go ahead and assume NAP mode. It doesn't matter.
NO MATTER HOW YOU WORK IT, RAMBUS IS A POWER HOG.
-- Carl |
