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To: John Walliker who wrote (29336)	9/12/1999 11:29:00 AM
From: Dan3	Read Replies (2) \| Respond to of 93625

Re: 90 ns is not a lot if it is invoked only occasionally... Applications are in their caches about 95+% of the time. When they do encounter a cache miss, what area of memory will need to be addressed next? I don't think that anyone has spent much time reviewing that issue yet, previous technologies had the same penalty for a cache miss no matter what region of memory was the next requested. What if it's a branch to the OS or another module half the time (as a starting point)? It's important to remember that a 667MHZ processor running 1.5x superscaler forgoes executing 90 instructions every 90ns. If most cache misses are branches to NAP mode rambus chips, the performance penalty could be the difference between: 63ns - 95 instructions executed 90ns/2= 45ns - NAP to ATTN every other cache miss 70ns - rambus 800 line read 178ns 63ns - 95 instructions executed 0ns - this time an active chip is addressed 70ns - rambus 800 line read 133ns That would cut system performance by 25%! Dan