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To: Dan3 who wrote (29346)	9/12/1999 7:09:00 PM
From: Bilow	Read Replies (2) \| Respond to of 93625

Hi Dan3; I am unable to understand your calculations for the performance due to using NAP mode instead of STBY mode on a cache miss. I think you have included execution of 95 instructions, and the time for the execution of those instructions, plus the time required to load the one cache line (or the first bytes from one cache line) from memory. It seems to me that this would indicate a cache miss rate of 1 instruction out of 95. The figure you quoted was that applications are in their caches 95% of the time, and this doesn't jibe with the 1 of 95 figure, which is close to 99%. Possible explanation. I think that the 95% figure is about correct, but it is a time measurement, not an instruction count measurement. The 5% of the time an application is out of its cache corresponds to far fewer than 5% of the total instructions executed. This is because instructions in cache execute a lot faster. (I have to admit, it's been a long time since I had to calculate hit rates on caches, and their effect on performance. I've been in memory system design for 15 years now, but mostly in video where this is not an issue, and maybe the hit rates have gone way down from what I remember. 15 years ago, I was in super minicomputers, maybe PCs are different beasts. But I have noticed that the techniques that were first used on big computers have migrated down to the low end, so my guess is that my intuition is correct. Your figures are showing the PC stalled about half of the time. If this is correct, I am amazed, I didn't know it was that bad, what with all the algorithms for look ahead cache fetching and what have you that have been announced over the years.) Anyway, assuming the 95% applies to time, rather than instruction count, this means that as you turn on and off the NAP feature, you will alter the percentage of time that the application is in cache. So I will assume that the 95% figure applies to the STBY mode. For STBY mode, the computer spends 95 seconds executing, and 5 seconds stalled, for a total of 100 seconds to do this work. For NAP mode, the computer spends 95 seconds executing, and 5 * (90+70)/70 = 11 seconds stalled, for a total of 106 seconds. Assuming that half the cache hits go to NAP, the other half to STBY mode, the average time required is (100 + 106)/2 = 103 seconds, for about a 3% performance hit. Leaving everything in NAP would mean a 6% hit. For machines that are battling out performance duels, 3% is a lot. (See the EE-Times article I linked earlier that noted that the 40% improvement in bandwidth between EDO and DRAM only resulted in 1 or 2% improvement in system performance, for example. Engineering is about taking advantages of those 3% differences, or at least understanding the tradeoffs involved. The notebook people care a lot more about power consumption. My guess is that they would gladly eat the 3% and go ahead and reduce power. You could even have an algorithm that tracked how many cache misses were happening, and adjust the STBY/NAP value accordingly, to squeeze a little more performance out. -- Carl

To: Dan3 who wrote (29346)	9/13/1999 5:03:00 AM
From: John Walliker	Respond to of 93625

Dan3, It's important to remember that a 667MHZ processor running 1.5x superscaler forgoes executing 90 instructions every 90ns. If most cache misses are branches to NAP mode rambus chips, the performance penalty could be the difference between ... That would cut system performance by 25%! It is up to the system designer to make the appropriate compromises between latency and power consumption. However, many applications will not use all the available ram, so I think my guess of half the devices being in NAP mode is perfectly reasonable. My PC has 256 Mbyte of RAM, but much of the time it only uses 80 - 120 Mbyte (running W2000 build 2072) with a few ordinary applications running. John