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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (29364)	9/13/1999 4:58:00 AM
From: John Walliker	Read Replies (2) \| Respond to of 93625

Kash, The error is in assuming that DDR-SDRAMs consumption is similar to RDRAM. DDR-SDRAM has essentially CMOS outputs and a CMOS load. The I/O portion of DDR-SDRAM consumes Zero current in the steady state when nothing is switching. In addition the current/power consumed in the I/O is NOT derived form the Iol/IOH and Vol/Voh specs. Power in CMOS switching is primarily consumed in driving capacitance - so it is a capacaitance/voltage/frequency calculation. In DRDRAM you have a DC component in the I/O as well as frequency component. So you take another look at your DDR-SDRAM power calculation. Take a look yourself at the data sheet for the IBM DDR RAMs we have been discussing. In it you will see the test load used to characterise the outputs. I used the component values in their test circuit as the basis for my calculation. It uses DC termination. Therefore current flows all the time. Do you not think that IBM expect their devices to be used in this way when they specify them thus? Do you really think that DDR RAM will work reliably with out termination? You are of course right that the real-life current in a DDR RAM system will be higher because of the energy dissipated in charging and discharging circuit capacitances on each data transmission. The neat thing about the Rambus design is that because great efforts have been expended in making the transmission line well matched, its impedance is truly resistive. The current needed to drive it will not therefore increase with frequency due to external circuit capacitances. There are no significant stubs adding capacitive reactance as with a DDR RAM SIMM. Also, when the Rambus bus is carrying logic zeros, it draws no current at all (apart from leakage currents). In contrast, with DDR there are some signals that cannot be tri-stated, so these signals will always be driving their termination resistors. Neither the DDR data sheet nor the Jedec standard for SSTL2 which Carl referenced gives any guidance on non-resistive termination. I stand by my methodology as being a reasonable approximation. If you really want, I could calculate the additional power used by DDR RAM under high frequency conditions. John