Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: John Walliker who wrote (29402)	9/13/1999 5:38:00 AM
From: Bilow	Read Replies (2) \| Respond to of 93625

Hi John Walliker; Re IBM's output load for AC Timing Parameters... Those of us who are familiar with how spec sheets are written know that part parameters are always tested in some form of worst case. In IBM's case, they chose a 25 ohm resistor into a 30pF capacitor to ground, then a 25 ohm resistor to Vtt. I fail to see the point behind that kind of "termination". In fact, it's not a termination suggestion. The 30pF capacitor models a high capacitance load. In actual use, the stray capacitance would be a lot less. All they are doing is showing that you can "arc-weld" with their output buffers. This has very little to do with how the part would be used in real life. If you want to know about termination options for SSTL_2, you have to go look at the data sheet for SSTL_2, not the output load for the IBM chip. You can look up the SSTL_2 definition on the Jedec web site. 4.1 Push-pull output buffer for unterminated loads In many applications where interconnections are short, there is no need for any termination at all. An example of this is shown in figure 6. This application can be served by a Class I or Class II type buffer and an SSTL_2 type receiver. jedec.org The whole idea behind SSTL_2 is to allow the driving of transmission line stuff, not to force it. Since the data lines in the design example at hand have only two pins, and very little capacitance, the push-pull type termination would be used. -- Carl

To: John Walliker who wrote (29402)	9/13/1999 12:06:00 PM
From: kash johal	Read Replies (3) \| Respond to of 93625

John, Re:"Take a look yourself at the data sheet for the IBM DDR RAMs we have been discussing. In it you will see the test load used to characterise the outputs. I used the component values in their test circuit as the basis for my calculation. It uses DC termination. Therefore current flows all the time. Do you not think that IBM expect their devices to be used in this way when they specify them thus? Do you really think that DDR RAM will work reliably with out termination? You are of course right that the real-life current in a DDR RAM system will be higher because of the energy dissipated in charging and discharging circuit capacitances on each data transmission." John if you look at any regular CMOS device the outputs are tested with a specific load. It goes back to the good old TTL days of specing outputs. Take a look at any SDRAM specs and you will see the same. So it is how they are tested and NOT how they are used in real life. Perhaps if you don't believe me are there any EE's who are long RMBS who can convince John. Calling Tench / Scumbria. regards, Kash