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Technology Stocks : Ampex Corporation (AEXCA) -- Ignore unavailable to you. Want to Upgrade?

To: killybegs who wrote (10947)	9/12/1999 4:53:00 PM
From: Hal Campbell	Read Replies (1) \| Respond to of 17679

Mighty interesting. Thanks Tom and Jubimer. For any here who might be both Ampex AND Redskin fans ....let me just say ( using both of Carl's suggested techniques ) %^$#@^&%#$% AAAAAAAARRRRRRRGGGGHHHHHHHHHHHHH ( you had to see the game to understand )

To: killybegs who wrote (10947)	9/12/1999 5:18:00 PM
From: Michael Olds	Read Replies (1) \| Respond to of 17679

Havn't we seen this before? I am certain that I have,unless it is very similar to another one.

To: killybegs who wrote (10947)	9/12/1999 5:44:00 PM
From: DrD	Respond to of 17679

Many thanks Tom and Jubimer. Judging from the abstract and this excerpt, it appears that this invention (Ampex) is again "pushing the envelope" for com/dec and the layering that is involved. Perhaps it is included in some of the improved streaming media technology to be released in the Fall by INEXTV. DrD

To: killybegs who wrote (10947)	9/13/1999 10:58:00 AM
From: don_lapre	Read Replies (2) \| Respond to of 17679

Jubimer - I believe most have overlooked the largest problem associates with Internet video -- buffering. Most people have also overlooked this 1997 Ampex patent. Key point: "In normal operation the Read Data FIFO 64 will be kept full enough (by setting the latency to be about 32 clocks) such that it will not become empty during the Refresh cycle pause. After refresh, read cycles continue and the Read Data FIFO 64 will be filled before the next refresh cycle, thus Read refresh occurs transparently to the user read process, such process continuing without gaps or pauses." Without GAPS or PAUSES. More: "This invention relates generally to a method and apparatus for controlling a buffer, and more particularly to a method and apparatus for controlling at least one bank of dynamic FIFO (first-in first-out) RAM memory for storage and retrieval of digitized data at real time rates." "The controller system controls the buffers to enable the continuous writing of user data to one of the first and second banks at a given address, with the user address and data synchronized to the write clock, while enabling simultaneous reading of data at a user provided address from the other of the first and second banks, with the loading of read addresses and outputting of read data occurring continuously and synchronously to the read clock. Refresh of the memory occurs when the read or write buffer is not full." 164.195.100.11 tiny