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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?


To: Tenchusatsu who wrote (29651)9/16/1999 12:57:00 AM
From: richard surckla  Read Replies (1) | Respond to of 93625
 
Ten, KZ, others...

(Clip)

>...At the Intel Developer Forum (Sept 1st 1999 in Palm Springs, CA) Jay Bell, Senior
Fellow of Dell Computer disclosed the first publicly released benchmark results for
the Rambus/Camino platform.

Though the results have yet to be independently verified, performance figures quoted
by Mr. Bell generally indicate that under normal conditions, Rambus degrades the
performance of Microsoft Office 2000 applications by an average of 25% as
compared to PC100. Using a benchmark called Office Bench,
Dell's engineers
contrasted a BX chipset platform using 100MHz SDRAM against a Camino platform
with 800MHz Direct Rambus. Other than DRAM and chip set, both systems were
configured identically with 500MHz processors.

The results in the charts and commentary below were graphically extracted from the
original presentation material delivered at IDF. Black and white scans of the original
charts are available....<

Does this mean that the DELL specs we have seen and been talking about show a "slowdown" only when running Microsoft Office 2000? I'm lost???



To: Tenchusatsu who wrote (29651)9/16/1999 8:39:00 AM
From: Dan3  Read Replies (2) | Respond to of 93625
 
Re: You're own words betray you. If the constraint is the video card...

This shows up when running resolutions greater than 640x480. I can post link if you need them, but you'll probably recall having seen such information before, if you think about it. There is a lot of interest in the benchmark community regarding Nvidia'a new card, because it is hoped that this card will be able to exercise current and near term future processors (and memory subsystems) better.

Dan



To: Tenchusatsu who wrote (29651)9/16/1999 2:44:00 PM
From: dumbmoney  Read Replies (1) | Respond to of 93625
 
Or at least could you point me to some technical papers describing VC SDRAM?

necel.com

Briefly, there are 16 row caches (actually 1/4 row). A row cache can be filled by any row in any physical bank. Core operations (e.g. precharge) occur concurrently with row cache read/write.

Incidentally, the VC concept is equally applicable to Rambus. It would solve the too-many-physical-banks problem they seem to be having.