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To: patrick tang who wrote (19999)	9/29/1999 9:27:00 AM
From: Paul Lee	Read Replies (2) \| Respond to of 25814

Synopsys and LSI Logic to Jointly Develop Models for Hardware/Software Co-Verification SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 29, 1999--Synopsys, Inc. (Nasdaq:SNPS) and LSI Logic Corp. (Nasdaq:LSI) have agreed to jointly develop high-performance, cycle-accurate models of popular LSI Logic microprocessor cores for hardware/software co-verification. The first model to be released under the new agreement is the TinyRISC EZ4102 MIPS compliant processor core. It is available immediately from Synopsys. Models developed under this agreement will be verified against the LSI Logic test suite to ensure their accuracy. Hardware/software co-verification with Synopsys' Eaglei(R) environment allows designers to significantly improve product quality and reduce design time by allowing application and OS software to be run on hardware long before physical prototypes are available. This capability is essential for successful verification of complex system-on-chip designs. Design teams who have adopted this methodology have typically reported design cycle reductions of at least 20%. The LSI Logic EZ4102 MIPS Processor architecture focuses on the cost-sensitive consumer electronics embedded market. With MIPS16 support for code compression, the EZ4102 is well suited for applications such as set-top boxes, digital TV, DVD, digital cameras, GSM digital cellular phones, small office/home office (SOHO) network routers, convergence PCs, and a wide array of emerging embedded applications including smart cards for banking, toll booths, and shopping; security ID, wireless communications, cable modems, and integrated automotive entertainment and control units. All of these end products have a significant software component, which must run in concert with the custom hardware, making early verification of the integration of the hardware and software design elements essential to achieve aggressive time-to-market goals. "LSI Logic has seen growing customer demand for a comprehensive verification tool suite, in addition to IP building blocks," said Karen O'Connell, director of LSI Logic's Consumer Products Division, "By combining Synopsys' model development technology and engineering expertise with LSI Logic's in-depth processor knowledge, we are able to efficiently meet the growing demand from our customers for access to the co-verification models they need for successful early integration of hardware and software." The open Synopsys Eaglei architecture ensures that the new LSI Logic EZ4102 model will be useful to designers using the widest available range of software development tools, real time operating systems and hardware design tools, including cycle-based simulators and emulators. The EZ4102 Eaglei model implements both 32-bit instructions and 16-bit instructions for code compression. It supports both big and little endian modes. The cache of the model is fully configurable both at simulation startup time and on the fly, to allow the user to simulate various EZ4102 cache configurations. Interrupt handling, MMU, internal write buffers, BIU and Cache Controller (BBCC) are also modeled. This allows software designers to accurately measure code performance and hardware designers to have a very fast, accurate model of the activity of the processor buses and pins. For more information on Synopsys model support for LSI Logic, contact your local Synopsys representative, email verify@synopsys.com or, in North America, call 800/346-6335.

To: patrick tang who wrote (19999)	10/13/1999 8:17:00 AM
From: Paul Lee	Respond to of 25814

Company Press Release SOURCE: LSI Logic Corporation Hitachi and LSI Logic Forge Technology Alliance TOKYO, Oct. 13 /PRNewswire/ -- Hitachi, Ltd. (NYSE: HIT - news) and LSI Logic Corporation (NYSE: LSI - news) today announced a wide-ranging technology agreement that calls for joint development and exchange of 0.10-micron device architectures, copper and low K interconnect, advanced lithography, direct write E-beam and technical cooperation on embedded DRAM. Research teams from both companies are already engaged in the U.S. and Japan in a variety of technology development activities. The first result of the alliance will be LSI Logic's embedded DRAM solution based upon Hitachi's process technology. LSI Logic expects to begin shipping system-on-a-chip products with embedded DRAM cores in mid-2000. ''We are excited to have the opportunity to team with system-on-a-chip leader, LSI Logic, on a variety of next generation process technologies,'' said Hitachi's Kunio Hasegawa, executive vice president of Semiconductor and Integrated Circuits. ''This comprehensive partnership will advance Hitachi's and LSI Logic's technology offerings and will be beneficial for both companies in serving their global customers.'' ''The strategic partnership utilizes the combined resources of two industry leaders to address the most costly and complex technology challenges associated with ever-shrinking geometries,'' said Joe Zelayeta, LSI Logic executive vice president of Worldwide Operations. ''The culmination of this alliance will maximize returns on R&D investments of the respective companies, while assisting both of us in meeting the ongoing challenges associated with the rapidly accelerating requirements of new technology.'' The two companies will contribute different technology strengths to address the issues associated with 0.10-micron designs and beyond. ''Both Hitachi and LSI Logic will be able to increase their market leadership by combining their technology strengths such as Hitachi's advanced process technology and LSI Logic's leading logic device technology,'' said Masahiko Ogirima, Hitachi senior vice president of Semiconductor and Integrated Circuits. For example, this partnership combines the experience of Hitachi in copper interconnect with LSI Logic's expertise in low K dielectric materials. The initial offering of the comprehensive alliance will be LSI Logic's embedded DRAM (eDRAM) product based upon Hitachi's 0.20-micron process technology and LSI Logic's CoreWare® design methodology. ''The eDRAM product is specifically designed to provide a cost-effective embedded DRAM solution for customers competing in the high-growth networking, telecommunications, wireless, computer, storage and consumer markets,'' said John Daane, LSI Logic executive vice president of Communications, Computer and ASIC Products. ''The combination of Hitachi's embedded DRAM technology and LSI Logic's library of intellectual property cores provides impressive offerings to customers that are building products for the rapidly growing Internet infrastructure.'' Technology Alliance Overview Joint development of advanced device architecture for 0.10-micron transistors including the performance, reliability and failure analysis techniques associated with these devices. Development of advanced interconnects for 0.13-micron devices, including copper interconnect and low K dielectric constant insulators for competitive integrated solutions. Development of 193 nanometer wavelength lithography, reticle technology, prototyping techniques for 0.13-micron technology and mass manufacturing. Combined research on direct write E-beam technology. An embedded DRAM foundry relationship in which Hitachi will manufacture wafers for LSI Logic, incorporating LSI Logic's intellectual property libraries.