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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (88651)	9/22/1999 4:22:00 PM
From: Rob Young	Read Replies (2) \| Respond to of 186894

< In comparison, I do know that the Alpha 21364's on-die L2 cache, which is 1.5 MB large, will have a latency of 12 clocks, compared to 8 clocks for Intel's Celeron. Some of the reasons cited for Alpha's long latency (according to MPR) include power savings (a significant factor when the CPU already consumes 100 watts) and the unwillingness to modify the 21264 core design. I guess in the case of Celeron, Intel could have improved upon its L2 latency, but didn't because of time-to-market reasons.> Yeah.. but the kids enjoy talking about MHz too but who cares about MHz. Tell me how well it performs, tell me about SpecInt95 and TPC benchmarks. So when you say: " In comparison, I do know that the Alpha 21364's on-die L2 cache, which is 1.5 MB large, will have a latency of 12 clocks, compared to 8 clocks for Intel's Celeron. Some of the reasons cited for Alpha's long latency" Wrong comparison. Let's look at wall clock time (atomic clock I guess) and you see that the time for load to use is 12 nsecs for those 12 cycles: digital.com And when the clock turns to 1.5 GHz (maybe introed at that .. ) we are looking at 9 nsecs: theregister.co.uk With L3 (yes L3.. Intel is attempting to change industry view with L0 and L1 and L2) at 1 GHz: "and cache throughput 4.5 times" Also.. an Alpha Box OEM states regarding the cache and 1.5 GHz CPU issue: "Actually, these are two different products; one is 'standard' EV-68 in 0.18um copper SOI at 1.5 GHz using 8 MB external L2 DDR-SSRAM (which can provide either 1 GHz or 750 MHz or 500 MHz data rate depending on budget), and integrated Samsung version which has no external cache, but built-in 2 MB of full-speed L2 cache (again 1.5 GHz) on-die! It also has only a 250+ pin package..." (There is your 9 nsec latency ... in this case a souped up 21264 running on-chip L2 full speed at 1.5 GHz and as you can see low-cost 250 pin and no need for L3 .. maybe 800 MHz RDRAM? Nice divide by two there. One wonders how much that box would cost and how well it would do.) Pretty much need a fast subsystem if the CPU is calling for 6 GByte/sec: digital.com --- Effeciency is a waste of energy. How well does it perform compared to the competition. Periodically, (about every 6 months) someone wanders into comp.arch and dredges up "SpecInt95 per MHz". It goes round and round for a while and dies out. Doesn't matter how effecient. Rob