Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Rob Young who wrote (88672)	9/22/1999 4:56:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Rob, no need to get all riled up. Here's the quote from MPR regarding the Alpha 21364's L2 cache: One potential problem is the L2 access time. Whereas the 21164 was thought to be deficient with a six-cycle access, the 21364 requires twice that. Even Intel's Mendocino, not exactly a paragon of performance, needs only eight cycles to access its on-chip L2 cache. Its impressive 80-entry reorder buffer notwithstanding, the 21364 is unlikely to queue enough instructions to avoid stalling during a 12-cycle L1 cache miss. I never said anything about performance-per-clock, and even MPR's article had to put in that little disclaimer regarding the comparison. All I said is that the L2 latency of Mendocino is 8 clocks, and I tossed up some theories as to why it isn't shorter by drawing some analogies to the Alpha 21364. Obviously, I would never be able to say that Mendocino Celeron can outperform an Alpha 21364 and keep a straight face. (Steve Jobs could if he worked for Intel, but that's a different story.) Tenchusatsu

To: Rob Young who wrote (88672)	9/22/1999 5:06:00 PM
From: Tenchusatsu	Respond to of 186894

Rob, <With L3 (yes L3.. Intel is attempting to change industry view with L0 and L1 and L2)> Big deal. It's just nomenclature. Intel just wanted to keep the name L2 for the last layer of cache before the FSB. If you wanted to be more precise, you could call them L1, L1.5, and L2, although I doubt that would go over well. (By the way, I usually think of L3 as a common cache on a motherboard that is shared by multiple processors.) I sure can't wait to see what an L(-1) cache looks like. Tenchusatsu