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Technology Stocks : AMD/INTC/RMBS et ALL -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (134)	9/28/1999 3:47:00 AM
From: Bilow	Read Replies (2) \| Respond to of 271

Hi KZNerd; Interesting article, about IC reliability, a topic on everyone's mind right now: September 13, 1999 Soaring test costs, market-timing pressures are redefining 'reasonable' reliability in the field In this new world, we may see IC reliability approach the model set by commercial software: Ship when functional, let early customers find the bugs, and update when marketing says it's appropriate. The old notion of best effort to verify that a chip is correct and failure-free may become-so to speak-a memory. Smells a little like Camino. I disagree completely. The software people have always lived in a pretend house, as far as manufacturing goes. The reason is that their production costs (not development costs) are so minuscule. They can afford to ship crap and then replace it for free, their stuff is too cheap. But even a mega-profitable company like DELL only makes a few pennies per dollar. So hardware companies just don't have the option of scrapping stuff regularly. Scrap is death to high volume, low cost, competitive manufacturing. I bet that the box makers are a lot more pissed with INTC and RMBS than they are letting on. I bet that they are absolutely furious, and are swearing to never get near RMBS again, and also to take a good look at AMD. The thing is, so many experienced engineers were saying that exactly this was going to happen. The following quote probably describes what happened to Camino. Rambus just rides too close to the edge, and the simulations aren't good enough to tell exactly where that edge is: "For 0.5-micron processes, the simulation models are very good, and you can expect to get about what the simulations say you'll get. But with the 0.18- and 0.13-micron processes some people are starting to use, the models have been extrapolated from previous processes and just haven't been iterated enough to be accurate," Allison said. "There are still timing and other issues that simulation won't predict, and you end up having to debug in silicon, and at full circuit speed." techweb.com P.S. It is generally agreed among the hot shot engineers I know that the problem is insufficient timing margin on the data bus. I bet that they fix this the same way they fixed the early SDRAM problems. (The ones that Rambus has been claiming can be avoided with their integrated management of the memory system design. Ha ha) They will require underclocking of the RDRAM. Even now, I'll bet they have tried this and it worked for them, they just don't want to give the performance hit, especially when the technology gives so few benefits already. -- Carl