Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Cirruslvr who wrote (73902)	10/4/1999 11:58:00 PM
From: Yousef	Read Replies (1) \| Respond to of 1572637

Cirruslvr, Re: " ... which I took to mean that even though the Athlon may have a high yield % ..." No Cringe, you missed the "point" that Elmer was making. Elmer was stating correctly that a larger die size will have a lower percentage yield than a small die AND it will also obviously have fewer GDPW. I think if you understood processing better, you would realize the significance of die size on die yield (%), GDPW and manufacturing cost. Tell me Cringe ... Will AMD move the K7 to a true .18um (FEOL & BEOL) process or will they wait for the Dresden "fiasco" ?? Make It So, Yousef

To: Cirruslvr who wrote (73902)	10/5/1999 12:09:00 AM
From: Bilow	Read Replies (1) \| Respond to of 1572637

Hi Cirruslvr; Re all this talk about yields... From an economic point of view, I think the best way to measure yield is by the ratio of used silicon area to total wafer silicon area. Sure you get fewer chips if they are bigger, but they have more stuff on them - what really matters is how much silicon you put in the recycle bin. The increase in integration generally provides benefits in terms of reduced total package costs, increased speed, decreased total power consumption, increased reliability, etc. Those advantages of increased integration are what have driven this industry to putting many millions of transistors on a chip. So I think the above ratio is the one to use. It is almost equal to the ratio of good die over total die, the difference being silicon area wasted at the wafer edge, or used for process control. If you use this metric for evaluating yield, you more or less (see note below) always conclude that the yield decreases when you increase the size of the die. But if the defect density is low enough (or the circuits have enough redundant logic), the penalty for combining two circuits into one chip can be very, very small, much smaller than the increased packaging costs of separating the two logic blocks. It's a complicated matter of engineering trade off, just like almost every other non-trivial engineering decision. Every foundry I've dealt with has been extremely reticent about sharing their defect density. Who knows what AMD is doing, maybe they told Anand, but I doubt it. If AMD isn't getting great yields, they sure aren't pricing their product as if that were the case. -- Carl P.S. Note that it is easy to show that there can be reasonable examples of die size, wafer size, and defect density, where an increase in the die size (all other things being "equal",) results in an increase in yield, as defined above. Being a mathematician, and loving a good problem, I'll let those of you who haven't written down the equations figure out how this could happen.