To: Cirruslvr who wrote (74000 ) 10/5/1999 12:53:00 PM From: Goutam Read Replies (5) | Respond to
Cirruslvr,AMD, in another shot at Intel, establishes powerful 64-bit platform , By Mark Hachman(10/05/99, 10:58:21 AM EDT), Electronic Business News: ebnews.com o Internally developed X86-64 bit micro-processor architecture. The chip's name is "Sledgehammer"o Expected to ship in 2001.o Design represents an evolutionary approach . It's a simple change when compared to a completely new infrastructure.o Manufacturability will be the main focus behind the design decisions.o Adding 64bit capabilities increases the die size only 5% over 104sq.mm of Athlon using .18u process.o Combination of a small die size and it's 0.18u process will allow the company to pack more than one X86-64 µp on a single die.o IEEE-compliant, triple-operated, double-precision floating-point instructions to eliminate the fp advantage of RISC chips over X86.o -- snippet from the article --- When pairing more than one microprocessor on-chip, AMD will use undisclosed custom logic to manage the infrastructure. Off-chip, however, AMD has designed the custom LDT bus for I/O and coprocessor chips. The LDT is a bidirectional bus, either 8, 16, or 32 bits wide; the bit width is negotiable at the device's initialization. Data passes through multiple logical channels in up to eight links or bridges, which can be connected to several daisy-chained devices.o AMD doesn't think OS support will be a problem.o Minimal infrastructure changes, would be of benefit to OEMs. "Intel took the Merced design and forced it on [the OEMs], said Bob Mitton, division marketing manager for AMD's workstation products. o Ron Curry, director of marketing for IA-64 products at Intel, Santa Clara, Calif., compared AMD's approach to souping up a Volkswagen with wider tires and a faster engine.o AMD is not going to pursue Slot B direction. However, Alpha Processor Inc., and Hotrail Inc., (may be Reliance Computer Corp.,) are expected to be the main chipset suppliers.o AMD showcased an 800-MHz running on .18u process.o Announced the consideration of k6-2+ (k6-2 with on-die L2 cache) using .18u, to complement Ultra Workstation/server chip planned to ship next year.o Athlon Ultra for Workstations and Servers will feature 1 and 2 Mbytes of off-chip, full speed, 16 way, set-associative Level 2 cache. 266MHz EV6 bus. Related chipsets will feature 66-MHZ, 64-bit PCI with 4X AGP Pro and a PC2100 DDR DRAM interface. o K6-2+ with 256, 128, 0 KBytes on-chip cache. 0.18u process. There would be other enhancements/details - will become clear in the fourth quarter, when K6 hits the 0.18 process.
