Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: tejek who wrote (74005)	10/5/1999 12:19:00 PM
From: Charles R	Read Replies (4) \| Respond to of 1573040

Someone at Intel gotto be very concerned. ebnews.com Apparently a 800MHz processor was demonstrated yesterday! Note the unnamed processor with built in L2. I wonder what it is ;-) Most importantly, not the part about not being concerend about software support for Sledgehammer. Gee, I wonder why ;-)

To: tejek who wrote (74005)	10/5/1999 12:27:00 PM
From: Cirruslvr	Read Replies (1) \| Respond to of 1573040

What we all want - Information Lots of it in this article - AMD discloses internally-developed 64-bit architecture (It's too long to post) ebns.com "Adding 64-bit capabilities increases the 104 sq. mm. die size of a 32-bit Athlon processor produced in 0.18-micron technology by only 5 percent, Lapinski said." So if the SH flops and its X86 is up to Willamette's par, AMD won't have a completely defunct processor with the K8 "More importantly, AMD claims that the combination of a small die size and its 0.18-micron process will allow the company to pack more than one 64-bit X86 microprocessor on a single die. That's important, given the fact that X86 integer instruction performance is closing in on RISC chips, Lapinski said. Through triple-operand, double-precision floating-point instructions that AMD is designing for the new architecture, the company hopes to eliminate the floating-point advantage of RISC chips as well, he said." I wonder if they are aiming at the 21364's FPU capabilities. I don't remember the number those guys are speculating, but I think it was 3 digit SPECfp95 score. Rob Young can probably comment on that. "One thing we haven't brought up is the software infrastructure" That's a biggy of course. "Next year, the Athlon Ultra for workstations and servers will feature 1 and 2 Mbytes of off-chip, full-speed, 16-way, set-associative Level 2 cache." "Lapinski also said AMD is evaluating the so-called K6-2 Plus, a 0.18-micron K6-2 reported to include 128 or 256 kbytes of on-chip cache. A third chip without Level 2 cache is also thought to be under consideration, although Lapinski would not divulge details"