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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Process Boy who wrote (74147)	10/5/1999 10:35:00 PM
From: Dan3	Read Replies (2) \| Respond to of 1572673

Re: Intel quadrupled the 64 bit cache line to 256, on die... Did they quadruple the cache, or the cache line? Weren't they already at 32 bytes (256 bit) for the cache line? I know the Pentium and Pentium Pro were: ============================================= support.intel.com Use Memory Read Line (MRL) for reads of data fitting within 1 cache line and containing more than 4 bytes (for which MR would be used). On Pentium© Processors and Pentium© Pro Processors a cache line is 32 bytes (8 Dwords). ============================================== If you mistyped and meant to put 256 bytes as the cache line length, it may not be the ideal size. There is always a trade off between longer and shorter cache lines. Too short and you miss many hits to the next serial address, too long, and you limit the number of lines in the cache. I'm not sure going to a 256 byte cache line is ideal. 32 bytes for a 32 bit processor seems to have been the sweet spot. (This is all way beyond me, I'm just listing what seems to be industry practice for CISC CPUs) That's why I was a little surprised to see that Athlon had gone to a 64 byte cache line - but if the design had been aimed at 64 bits from the begining, then a longer cache line might have made more sense - it would allow for the same 8 serial accesses to memory on cache hits. Dan