Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Process Boy who wrote (75829)	10/18/1999 1:50:00 AM
From: Charles R	Read Replies (1) \| Respond to of 1571813

PB, <extremely tight pitches and added process complexity add inherent yield loss mechanisms and cost vs. non-local interconnect technology.> Is this a theoretical statement or has it been tested in the fab or is this something that you say based on AMD/IBM's experience from local interconnect. (I guess AMD travails with the K6 may indicate that there may be something to the "yield loss mechanism" angle though K6's problems itself were more design related than process related.) <For Intel's model, local interconnect is viewed as unnecessary and undesirable, at least from a process stand point. > Any speculation on why AMD may have found this desirable or necessary? If my memory serves me right this decision was made when AMD moved Nexgen's products from IBM's fab to AMD's fab (Did IBM have a 4LM and AMD 3LM and AMD used local interconnect to make for the missing metal?) Chuck