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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Charles R who wrote (76487)	10/22/1999 12:29:00 PM
From: Jim McMannis	Respond to of 1570087

The making of a Silicon chip by Intel, what Paul and Yousef had forgotten... intel.com I like this section...perhaps "Penang" Paul and "Rio Rancho" Stockman will be proud... "At an Intel plant in Penang, Malaysia, after a battery of sophisticated tests, a technician visually inspects a tray of finished processors before they are sent to a warehouse and used to fulfill customer orders. The culture behind the scenes of chip fabrication is perhaps the most fascinating element of the process. The world's largest "fab," or chip fabrication factory, is in Rio Rancho, New Mexico, where production never stops, and the clean rooms alone cover the area of three football fields. An otherworldly atmosphere plays host to the technicians, who spend their 12-hour shifts encased in GORE-TEX® "bunny suits." Workers wear this required garb over their clothes to keep minute particles such as dead skin cells from contaminating the microscopic circuits."

To: Charles R who wrote (76487)	10/22/1999 12:42:00 PM
From: DRBES	Respond to of 1570087

re: "most insiders already concede the race is lost at least until Wilamette" GOLLY! I wonder if AMD will be standing still until wilAMETTE is introduced so that intEL may catch up. Regards, DARBES

To: Charles R who wrote (76487)	10/22/1999 12:49:00 PM
From: Ali Chen	Read Replies (4) \| Respond to of 1570087

Charles, <the race is lost at least until Wilamette.> I have some doubts here. We know that the frequency "turbocharging" is done by superpipelining, or increasing the number of CPU pipeline stages. However, there is a limit: you can't make stages shorter than certain amount of gates deep - you still need to perform some "atomic" logic operations that cannot be sup-pipelined any more. You can't break it down to one-two NAND gates. Therefore, for a certain process technology stage, the frequency must be limited by these "atomic" functions, plus interconnect delays on long routes. In addition, longer pipelines have adverse effect on general code performance. Are there any indications that there is any significant room for super-super-pipelining left for Williamette? Why we think that Williamette can break laws of digital logic and physics? If not, and if the optimal pipeline length for x86 architecture was found to be about 10-12-15 stages, there is little reason to believe that any other re-shuffling or partitioning of prefetch, decode, execute, and retire functions will result in much faster and better performing x86 CPU than AMD Athlon or Intel CuMine. Any thoughts? (ignorant morons like Elmer, Paul, and Youseless are asked to not bother).