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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (76491)	10/22/1999 1:06:00 PM
From: Tenchusatsu	Respond to of 1579728

Ali, the general view at the Microprocessor Forum seemed to be that longer pipelines are a waste. I think even Merced was criticized for having a 10-stage pipeline, which some people thought might have been a little long. Of course, those same people stand to gain a lot from anti-Merced FUD, but the point seemed to be a valid one. So I guess if Willamette really does have an "Alaskan pipeline," it would run contrary to conventional wisdom at MPF. It will be interesting to see, no doubt. Tenchusatsu

To: Ali Chen who wrote (76491)	10/22/1999 1:09:00 PM
From: Charles R	Read Replies (2) \| Respond to of 1579728

Ali, If you note my language I say "the race is lost atleast until Wilamette". All I am (and architectural folks at and outside of Intel are) saying is that Wilamette provides a chance to pull ahead. To be sure only the exact performance potential is only known to a small set of people who understand all the trade-offs. However, it is clear that Intel is trying some interesting stuff that has nothing to do with superpipelining - like multi-threading, split-speed Integer/FP units, dynamic frequency changes, and some very interesting analog circuits to precision tune the pipeline frequencies. From what I understand, this "neat stuff" has already cost the program a lot in terms of time-to-market and there is good chance that it will cost some more at verification time. There are some mixed signal elements here that are not too conducive to simulation. The rubber needs to hit the road before the impact is clearly known.... Now, by the time Wilamette sees the light of the day, Athlon core would have progressed and there would likely be some compelling advantages in terms of smaller die, lower power, potential to build in massive amounts of cache or put a second processor on same die, etc., that could help AMD. But, that is probably more than a year away and usually there is not much point looking that far out. Right now, I am sticking with the "no contest until Wilamette" line. Chuck

To: Ali Chen who wrote (76491)	10/22/1999 2:13:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1579728

Ail - My Little ScrewDriver Buddy !!!! Re: " Are there any indications that there is any significant room for super-super-pipelining left for Williamette? Why we think that Williamette can break laws of digital logic and physics?...Any thoughts? (ignorant morons like Elmer, Paul, and Youseless are asked to not bother)." How about the extensive use of Domino Logic? Paul

To: Ali Chen who wrote (76491)	10/23/1999
From: THE WATSONYOUTH	Read Replies (1) \| Respond to of 1579728

Re: "If not, and if the optimal pipeline length for x86 architecture was found to be about 10-12-15 stages, there is little reason to believe that any other re-shuffling or partitioning of prefetch, decode, execute, and retire functions will result in much faster and better performing x86 CPU than AMD Athlon or Intel CuMine." Ali - What's your take on Moto repipelining the PowerPC design? (currently 4 stage to I believe planned 8 stage) Would you expect significant higher MHz. How much?? Any guesses? Currently, it can only achieve 500MHz in .25um vs. 600MHz for 12? stage PIII. Clock for clock, it outperforms PIII. THE WATSONYOUTH