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To: Saturn V who wrote (92424)11/14/1999 11:47:00 PM
From: THE WATSONYOUTH  Read Replies (1) | Respond to of 186894
 
Re: "Do you have any idea how the novel notch is implemented. ? What kind of gate(CoSi/polysilicon) etching procedure will give rise to the notch with the necessary precision and control ?"

Of course, this is all conjecture on my part, but a topic for interesting discussion. I could envision AT LEAST two approaches. One would be to use a two step etching process for the gate definition. The first step would be an anisotropic selective poly etch which also passivates (leaves a very thin SiOxClxBrx residue) on the sidewall of the etched feature. At a known thickness before the gate oxide is reached, the RIE process is changed to an isotropic selective etch process. You can employ laser interferometry
to indicate rather precisely when to switch processes. The isotropic etch process etches the remaining poly (creating the notch) with high selectivity to gate oxide. The sidewall passivation on the previously etched poly in step 1 prevents any sidewall erosion of that surface. The pictured profile will result. Dummy poly gates are added locally as needed to largely equalize the local poly etch pattern factor over the entire wafer. This kind of post processed data manipulation (not in the original design)is becoming very common. This local pattern factor equalization will, in theory, result in a uniform notched profile across the wafer. I'm sure the question of how this profile is controlled will come up at IEDM. I doubt if Intel will give
significant details. Another approach would be a DAMASCENE
process which, for brevity, I will not go into. I did see an Intel patent for such a process. I'm sure other people can think of other ways. I don't know if Intel is actually using this notched process for Coppermine or if they will use it only for the fastest parts (>900MHz) some time in the future. I haven't had access to a Coppermine SEM cross section yet. It would certainly be obvious.

THE WATSONYOUTH