SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (80663)11/21/1999 11:13:00 PM
From: Bill Jackson  Read Replies (1) | Respond to of 1584307
 
Elmer, I was of the opinion that the first 64K of cache gives you about 75% of the maximum potential of cache and that going to 128-gives~85% 256K-~92% 512K--95% on typical tasks, of course some will be better and some will dump cache every instruction. If this is the case why not at least make a smaller, but full speed cache onboard? I suspect it is partly a real estate issue and partly a process issue because memory and CPU might differ in process in some way not known to me, as it they could they would.Defects would hit CPUs as hard as Memory layouts?
Bill



To: Elmer who wrote (80663)11/22/1999 2:32:00 PM
From: Petz  Read Replies (1) | Respond to of 1584307
 
Elmer: re:<is there any good reason that AMD did NOT put the L2 on-chip in the aluminum 0.18 Athlons?>

Defect density is a good place to start speculating. To be effective it would need to be 4x the L1. That would make it 512K. AMD can't seem to manufacture the K63 with only 256K on die L2...

But the AMD roadmap seemed to imply that L2 would be integrated on copper-interconnect Athlons. Why should putting 512K L2 on die be any easier on a totally new process (Cu interconnect)?

Petz