Think I spotted it. Imagine the result if some bearish analyst sent the following paragraphs to several institutional customers who couldn't tell the difference between a DUV Laser and a light bulb...
Bell Labs researchers will go to IEDM to report progress on a vertical transistor approach that might lead the industry away from photolithography techniques. The 50-nm vertical gate was created by controlling the deposition thickness of polysilicon, rather than by using photolithography to define the gate dimension.
The vertical transistor "could supersede the conventional transistor" in about 10 years, according to Bell Labs -- an interesting claim from the laboratory that invented the transistor more than a half-century ago.
The Death of Optical Lithography has been 10 years away for the last 3 decades. I doubt that that will change in the next 3 decades.
I have to agree, if this story is the cause of the selloff, then we've got a pretty solid buying opportunity. Any chance that some institution will let me pick up some shares in the 20s? ;-)
Perhaps, the institutions need to review the stats on just how many very exciting lab technologies remain precisely that - lab technologies, never ever to see the light of a production fab floor.
Ian.
Whole story at:
semibiznews.com
and for the archives, here it is:
Researchers probe transistor's future at IEDM
By David Lammers and Peter Clarke
EE Times
(11/29/99, 01:08:00 PM EDT)
WASHINGTON ( ChipWire) -- The International Electron Devices Meeting, which convenes here this week, will take up the increasingly serious question of just how far solid-state electronics can be pushed before reaching the limits of physical speed and size.
In an effort to answer such questions, IBM Corp. will show a 50-nm device with what it claims is the fastest CMOS switching performance to date, and Intel Corp. will describe a device made at 0.10-micron design rules. Lucent Technologies Inc.'s Bell Labs, for its part, will present a "vertical transistor" that could eventually succeed today's devices and could resolve some of the lithography and materials problems of scaling CMOS to deep-submicron territory. That's significant because some researchers now predict a breakdown in gate oxides at the 130- to 100-nm level.
This year's IEDM is the 45th such conference, and the 220 papers presented over the three days from Dec. 6-8 will offer attendees a look at some of the most creative work being conducted in the world's semiconductor research laboratories.
A late paper from IBM's Watson Research Center in Yorktown Heights, N.Y., describes devices fabricated at 50-nm design rules that were created with very low threshold voltages. The low-Vt devices were used to create a 101-stage CMOS ring oscillator, which has a gate delay per stage of 6.4 picoseconds at -100øC -- the fastest CMOS switching performance reported to date.
At room temperature, the low-Vt devices operate poorly, but when taken to -100øC, performance is twice that of comparable room-temperature devices. Low-temperature CMOS has current-on and current-off characteristics that cannot be duplicated at room temperature, IBM researchers said.
Intel researchers will present some of the fastest CMOS transistors ever created. Using 0.10-micron (100-nanometer) design rules in a 16-Mbit SRAM "learning vehicle," the researchers achieved speeds exceeding 1 GHz. Power consumption was kept within acceptable limits, even with drive currents of 1 microamp per micrometer for the n-channel MOSFET and 0.45 microamp for the p-channel MOSFET.
In another late paper, Fujitsu Ltd. researchers describe a direct-tunneling memory that is similar to a flash memory device but with a floating-gate structure and sidewall-control gate architecture. The structure is applicable to embedded memory. By controlling the thickness of the tunnel oxide layer between the floating gate and the source-drain, control can be varied between data retention time and write time.
Bell Labs researchers will go to IEDM to report progress on a vertical transistor approach that might lead the industry away from photolithography techniques. The 50-nm vertical gate was created by controlling the deposition thickness of polysilicon, rather than by using photolithography to define the gate dimension.
The vertical transistor "could supersede the conventional transistor" in about 10 years, according to Bell Labs -- an interesting claim from the laboratory that invented the transistor more than a half-century ago.
Built on top of the silicon substrate, the vertical transistor has two gates -- one on each side of the channel-- opening the door to faster speeds. Bell Labs researchers first disclosed the work in April and will go to IEDM with claims that the vertical approach may resolve two scaling problems facing conventional transistors: the need for ever more expensive lithography tools and the difficulty in creating a thin, reliable gate.
In terms of basic technology, deposition of the gate oxide has emerged as perhaps even more challenging than lithography. The stage for IEDM was set several weeks ago in Belgium, at a technology symposium organized by Europe's largest microelectronics research consortium, the Interuniversities Microelectronics Center (IMEC), of Leuven, Belgium.
"Based on [the] temperature dependence of oxide breakdown, our results indicate that oxide reliability may already be a potential showstopper at 130 to 100 nm," said IMEC's vice president of silicon process technology, Luc Van den Hove.
The breakdown voltage of ultrathin gate oxides was especially discouraging at higher temperatures, leading Van den Hove to conclude that below a 2.5-nm thickness, the reliability of gate oxides may be worse than previously understood.
At IEDM, Bell Labs researchers will report encouraging results concerning gate oxide reliability at the 50-nm regime. Betty Weir, Mohammed Alam and other researchers working at the Murray Hill, N.J., lab have concluded that reliable gate oxides of less than 20 angstroms (2 nm) can be created using silicon dioxide.
"At 1.6-nm gate oxides, we are confident [of operation at] 1.38 volt; with further work, we believe that can be extended to 1.2-V operation at 70øC," Weir said.
That is a significant improvement over the 1.7-V operation that the Bell Labs team reported in an early version of the paper, based on results of just six months ago, she added. The experimental work draws on modeling by Bell Labs' Jeff Bude of the damage caused by electron hole injection.
Steve Hillenius, who heads the ULSI device technology research department at Bell Labs, said the progress achieved by Bell Labs and others might push out the need for alternatives to gate oxide materials.
Demonstrating effective gate oxides using silicon dioxide in the range of 16 to 20 † (1.6 to 2 nm) "will increase the difficulty of finding an alternative dielectric material" that improves on SiO2 in terms of performance, leakage and reliability, Hillenius said. In other words, silicon dioxide may be tough to beat.
Nevertheless, the search is on for new materials. DRAM capacitors may be the first area where SiO2 is replaced, with logic gates coming later. IBM researchers have concluded that "in the labs, we are working very close to the limits of dielectric reliability," said John Warlaumont, director of silicon technology at IBM.
"We can create oxides at 1.5 or 1.2 nm, but it all depends on the reliability the customer demands, and different customers have different reliability requirements,? Warlaumont said. ?What is the number we have to stop at? How far can we go with SiO2? It depends on reliability requirements. But there is urgency, because we may need a new gate dielectric material in five years.
"My feeling is that of all the many candidates to replace SiO2,? he continued, ?the best ones will be the simpler materials and not the complicated materials, such as the BSTO [barium strontium titanate oxide] materials being considered for DRAM capacitors.?
In Europe, IMEC is collaborating with ASM International BV Bilthoven, the Netherlands, on atomic-layer chemical vapor deposition (ALCVD) for gate dielectrics and metal gate deposition. The work with ASM International is linked to an IMEC Industrial Affiliation Program. Other companies are being invited to join to investigate high-k dielectrics and metal gates for 100-nm and smaller devices.
IMEC has also initiated a major European collaborative research program called HUNT (for hundred-nanometer CMOS technology) with Infineon Technologies AG, Philips Semiconductors and STMicroelectronics as part of its 100-nm integration program. HUNT is a broad program but will include research into gate-stack materials. HUNT will encompass 45 person-years of effort and will be worth about $10.5 million, with the European Union providing 50 percent of the funds.
Atomic-layer CVD deposits atoms layer by layer, resulting in nearly perfect thickness and uniformity over large-area substrates. "We therefore aim to use this technique to deposit very thin high-k dielectric layers and their silicates for use as alternative gate dielectrics," said Van den Hove.
The program will be based on work pioneered by Microchemistry Ltd. of Helsinki, a small research group ASM International acquired in July. |
