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To: Tenchusatsu who wrote (93280)	12/1/1999 6:32:00 PM
From: Tony Viola	Respond to of 186894

Ten, on-die L2, AMD had problems when they added an on-die cache to the K6-2 core and called it K6-III. Either yields were too low, or die size was just too large causing unit shipments to drop, or demand just wasn't there. That's what I recalled. Getting a little "colorful" with the nicknames, huh? Thunderthighs. I used to know a...oh nevermind. Tony

To: Tenchusatsu who wrote (93280)	12/1/1999 7:16:00 PM
From: Road Walker	Read Replies (2) \| Respond to of 186894

CNET's take on the coppermine problem: yahoo.cnet.com Not the execution we expect from Intel. The AMD thread would say it is the pressure of a competitor breathing down their neck, rushing a product launch. I have to wonder, with the new business opportunities in networking and data farming, if management isn't as focused on the core business? John

To: Tenchusatsu who wrote (93280)	12/1/1999 8:59:00 PM
From: THE WATSONYOUTH	Read Replies (1) \| Respond to of 186894

Re: "AMD had problems when they added an on-die cache to the K6-2 core and called it K6-III. Either yields were too low, or die size was just too large causing unit shipments to drop, or demand just wasn't there. Or perhaps it was a combination of all three. In any case, K6-III (which even beat Pentium III in a few office benchmarks) became a non-issue. By the way, I believe AMD is scheduling their Thunderbird core (Athlon w/ on-die L2 cache) to be released in Q2 2000. Not sure how quickly they can ramp production on that bad boy, considering that AMD only has one fab to work with (I don't think Fab 25 will be producing any Thunderthighs.)" I don't know the history of AMD and on die L2 except what I read on these threads. However, it seems to me from a random defect density point of view, if AMD is able to achieve acceptable yields at 184mm2 in .25um, they should be able to add L2 on die (256K ??) without a significant problem at .18um. Probably, (in the past) they had some sort of SYSTEMATIC defect associated with the cell design/process design that resulted in very low SRAM yields. Such systematic defects(especially in the SRAM cell) are certainly fixable and should not be confused with random defect density. I would not count on AMD not being able to achieve on die L2 cache. Just my take. THE WATSONYOUTH