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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (93289)	12/1/1999 9:46:00 PM
From: Saturn V	Read Replies (1) \| Respond to of 186894

Ref- <I don't know the history of AMD and on die L2 except what I read on these threads. However, it seems to me from a random defect density point of view, if AMD is able to achieve acceptable yields at 184mm2 in .25um, they should be able to add L2 on die (256K ??) without a significant problem at .18um. Probably, (in the past) they had some sort of SYSTEMATIC defect associated with the cell design/process design that resulted in very low SRAM yields. Such systematic defects(especially in the SRAM cell) are certainly fixable and should not be confused with random defect density. I would not count on AMD not being able to achieve on die L2 cache. Just my take> I agree with you. The biggest problem with the K6-3 was that it offered a minor performance improvement over the K-62, and that the market associated AMD with the value segment, and was not willing to pay a significant premium for the K-63.The K-63 also arrived when the 0.25 microns yields had tanked [ because AMD was trying to crank up the MHz by shrinking the poly] , and AMD could not afford the higher die cost. Obviously all that has changed. The K-63 on 0.18 micron becomes a more viable product. I see no technical obstacle to limit AMD from adding the L2 to the Athlon. It will again come down to the yield loss, and balancing the extra cost versus the performance enhancement and ASP. Again the execution of AMD's new technologies is not trivial, but right now AMD is on a three month winning streak. Intel will have to leap ahead of the Athlon by getting Willamette out early, or by further device scaling and design tweaks to the Coppermine.