Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (83098)	12/15/1999 2:01:00 PM
From: Jim McMannis	Read Replies (2) \| Respond to of 1571030

SAMPLE? CAN ANYBODY SAY SAMPLES? from the YUK... theregister.co.uk Posted 15/12/99 3:59pm by Mike Magee Intel will sample 800MHz Pentium IIIs next Monday Chip giant Intel will provide samples of 800MHz Pentium IIIs to its OEMs at the beginning of next week and will also announce several flavours of other of its desktop processors. The 750MHz Pentium III parts which were intended for release in January next year, will also be announced, sources close to Intel's plans have confirmed. But although Intel is likely to make a very big splash about the fact that it has a 800MHz Coppermine part and also Coppermine 750MHz parts, the whole question of this announcement raises several important questions. Providing samples to its OEMs -- the major PC manufacturers -- is not the same as supplying the chip in volume. The experience of people attempting to buy a 733MHz Coppermine Pentium III since October 25 bears witness to that. PC vendors will take time to evaluate the processors before they can build the 800MHz chip into their machines. There is a school of thought which thinks that Intel only started to sample its 733MHz processors shortly after it "announced" the 7xx processors at its last Developer Forum, in Palm Springs, in September. The 750MHz parts, however, will start to appear rather sooner than the 800MHz. We can expect to see 800MHz chips in machines round about February or March, in line with Intel's revised roadmap. As we correctly predicted last month, these Pentium III 750MHz parts cannot use the 133MHz front side bus (FSB). They will use the 100MHz multiplier bus, because of the basic rules of clocking things up. There are two flavours of the 750MHz part however, one being Slot 1 and the other using the infamous flip chip packaging. The two stories referenced below give details of the changes that Intel was going to make in January, but has now brought forward. Once more it appears that Intel has decided to take the marchitecture rather than the architecture route, possibly panicked into such action by AMD's success with the 750MHz Athlon which is available in large volumes. When Chipzilla panics, its great big galumphing feet can go in any direction that chaos theory doesn't predict. ® ------ Yep, INTEL is scrambling! Announcing a chip with only samples to an OEM? Are they serious? Did they learn this from Otellini?

To: Tenchusatsu who wrote (83098)	12/16/1999 12:38:00 AM
From: Dan3	Read Replies (1) \| Respond to of 1571030

Re: If you have to ask, then you know NOTHING about servers... Maybe not, but lets look at the possible loads on 1 DDR channel, just for fun. DDR 266 bursts pages at 266 * 64 = 17 gigahertz as a serial data stream or 266 * 8 = 2.1 gigbytes per second. The first use that comes to mind (granted, to one who knows NOTHING about servers) is pumping web pages out of DRAM if your server has a big pipe. What can a big pipe handle? Well, the current backbone of the internet is made up of DS-3s, OC-3s, and some OC-12s. A few OC-48s are starting to show up, and in the time frame we are looking at (a year from now), OC-96 should be on line between some some of the primary NAP (Network Access Points). So lets say your server is one hop away from the West Coast NAP, with an OC-96 connection to it, and all of your content is in RAM - how fast should your memory be? Well, an OC-96 connection will have a theoretical speed of 51.833 * 96 = 4,976 mbits/sec or about 5MHZ as a data rate. TCP/IP over the internet won't be 100% "efficient", but I'll give you the benefit of the doubt on that one. Now returning to the original 17MHZ serial data rate that a single DDR DIMM can burst at, it should be capable of saturating the theoretical maximum capacity of the largest Internet link that will be up during the next year even if it runs at less than 30% of its burst rate. Obviously, you will need an AMD LDT class of system bus to connect that DIMM to a set of NICs, but the bottleneck will be the system bus, not the DRAM bus. A good site for Internet backbone info is here: boardwatch.internet.com How about databases? If you have a serious application, you'll have a large fiber channel disk array pumping data at your memory bus. How fast would that be? Ciprico has a nice unit: fibrechannel.com that will burst data at up to 100Mbytes/second - and stream it at 90. But looking up at our initial calculations, we see that our one DIMM supports bursts at 21 times that speed. Three such arrays on a system could bring the data load up to 300Mbytes/second, one seventh the capacity of a single DIMM. If the "efficiency" of DDR is only 30%, we are still OK. If the system is running a lot of substantial CGI, ASP scripts, etc., it will be running many concurrent processes, and be heavily accessing memory as it executes the various tasks and swaps them in and out. But the accesses will be primarily short burst accesses where latency is very important. I would think that streaming large blocks of data for an extended period (where rambus could shine) probably won't be a common occurrence. Dan

To: Tenchusatsu who wrote (83098)	12/16/1999 12:33:00 PM
From: Bilow	Read Replies (1) \| Respond to of 1571030

Hi Technusatsu; Re Carl's posts on pin costs... I must have posted a dozen long, detailed posts, with internet links on this subject. The IBM example of a 5000 pin package is an example of a leading edge technology, a technology that was impossible until recently. But that is only one of at least a dozen links I gave about pin costs. It is very clear that pin costs have dropped over the years, not as fast as Moore's law for transistors, but nevertheless consistently. Standard DRAM used to be x1 width, now it is more like x8 and x16 are available at the same price. But the really important thing about pins is that the new bump technology eliminates the need to bond each pad individually. It is quite obvious that this improvement in automation is going to drop the cost of pins to a very small fraction of the current cost. -- Carl