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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (91734)	2/5/2000 6:47:00 PM
From: Cirruslvr	Read Replies (2) \| Respond to of 1576865

Tench - RE: "Yet another myth perpetuated by the AMDroids. Yes, Coppermine's on-die cache only transfers data every other clock. (What more do you need when you transfer a full 256-bit cacheline in one gulp?) But the cache is STILL full-speed. It's not like the transistors run at half-speed or anything. That's ludicrous." Actually, Saturn V posted here that the MPR said the cache is half-speed. Should the folks at MPR short Intel now? ;) Message 12262325

To: Tenchusatsu who wrote (91734)	2/6/2000 12:56:00 AM
From: Dan3	Read Replies (2) \| Respond to of 1576865

Re: Coppermine's on-die cache only transfers data every other clock. (What more do you need when you transfer a full 256-bit cacheline in one gulp?).. Your post raises an interesting point. I posted here some months ago speculation that the cache added to coppermine(that results in it being competitive with Athlon) may have been "borrowed" from the Willamette design. Which would mean that we've already seen a nice chunk of Willamette's performance improvement. I know that you (and others) scoffed at that idea, but now you are pointing out that the coppermine cache doesn't make much sense as a match to the PIII core that it's been attached to - are you sure that that cache wasn't taken from Willamette (or Itanium)? Are you in a position to know such things? Dan