SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (91762)2/5/2000 10:07:00 PM
From: Jim McMannis  Read Replies (1) | Respond to of 1576894
 
RE:"There is no particular reason why the fpu and integer units need to run at the same speed. In fact, most processors have the ability to run the fpu at 0 MHz when not in use."...

Thanks, even for the humor.

Jim



To: Scumbria who wrote (91762)2/6/2000 12:36:00 AM
From: Ali Chen  Read Replies (1) | Respond to of 1576894
 
Scumbria, <why you would want to run the L2 faster than the core. The core can only absorb data so fast,>

I depends on how wide your fetch window is relative
to the L2 width.



To: Scumbria who wrote (91762)2/6/2000 2:06:00 PM
From: Charles R  Read Replies (1) | Respond to of 1576894
 
<I can't think of any reason why you would want to run the L2 faster than the core. The core can only absorb data so fast, and the caches need to be balanced to optimize the relationship.>

Depends on your definition of "core", no? If you have a IF/scheduler that can parcel out multiple full speed instructions to the execution units then one could benefit from a cache that has the bandwidth to support these units. Especially in a "multithreading" kind of environment.