Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Bill Jackson who wrote (92039)	2/8/2000 8:46:00 AM
From: Process Boy	Read Replies (1) \| Respond to of 1576197

Bill - <Where does GaAs stand as a CPU material for an item of the complexity of the Athlon/P-III and what are it's prospects?> As far as I know, GaAs is nowhere on the near term radar screen for high volume MPU manufacturing. I defer to a device physicist for coherent explanations on why GaAs is unsuitable. I can think of some draw backs wrt manufacturing: 1) wafers are very brittle, and 2) expense. I'm sure there are more reasons than this. PB

To: Bill Jackson who wrote (92039)	2/8/2000 8:57:00 AM
From: Dan3	Read Replies (4) \| Respond to of 1576197

Deathstar, is bang on course to produce Cu-Athlons starting from now. Interesting choice of names. If .13 feature size with .05 gate length is a simple shrink away, I suppose the name might be appropriate - shouldn't that give us about 2GHZ for this year's holiday selling season? theregister.co.uk Regards, Dan

To: Bill Jackson who wrote (92039)	2/8/2000 11:56:00 AM
From: Pravin Kamdar	Read Replies (1) \| Respond to of 1576197

Bill, GaAs wafers in themselves are very expensive. The higher carrier mobilities and saturation velocities of GaAs, wrt silicon, in conventional FET structures (such as those used in microprocessors) are not enough to outweigh the extra cost and the immaturity of FET processing technology (larger sized devices). A real speed benefit comes by using expensive MBE and special CVD techniques to build super high speed bipolar devices, such as HBTs, by carefully introducing Al into the lattice to "bandgap engineer" junction potential barriers. But I haven't researched this area for about 10 years, so a lot may have improved in terms of GaAs FETs. Pravin These energy discontinuities at the junctions limit the reverse injection of minority carriers, thus allowing the base region to be extremely highly doped while maintaining gain (the device's ability to amplify). The highly doped base (at solid solubility limits) can then be made very thin for fast carrier transit times (high frequency) while maintaining low base resistance.