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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (92861)	2/13/2000 1:53:00 AM
From: milo_morai	Respond to of 1574004

850Mhz Link on PriceWatch.com queen.pricewatch.com+AND+%22ATHLON%22+AND+%22850%22&CiCodePage=Windows-1252&cr=AMD+Athlon+850 aceshardware.com Athlon News (AMD) Posted By Brian Neal Saturday, February 12, 2000 - 8:22:27 PM This is a pretty broad update to cover the Athlon-related news I've been missing for one reason or another: First off, thanks to Idiot for letting me know that AMD has updated the Athlon Optimization Guide amd.com so it now includes instruction latency information. Thank you AMD for bringing that back! Thanks to JC for noticing that the Athlon 850 queen.pricewatch.com+AND+%22ATHLON%22+AND+%22850%22&CiCodePage=Windows-1252&cr=AMD+Athlon+850 has made an appearance. The PIII-800 has also finally made an appearance on Pricewatch . queen.pricewatch.com+AND+%22PENTIUM%22+AND+%22800%22*&CiCodePage=Windows-1252&cr=Intel+Pentium+800 Speaking of fast CPUs, AMDZone posted a review amdzone.com of the Sys Cold Fusion 1000 (1 GHz Athlon Kryotech unit).

To: Scumbria who wrote (92861)	2/13/2000 2:16:00 AM
From: Scumbria	Respond to of 1574004

Correction: I said: 2-way would use address bits 20:5 to select the cache index, and bits 31:21 for the tag. 16-way would use address bits 17:5 to select the index and bits 31:18 for the tag. Actually: 2-way would use address bits 15:5 to select the cache index, and bits 31:16 for the tag. 16-way would use address bits 12:5 to select the index and bits 31:13 for the tag. Scumbria

To: Scumbria who wrote (92861)	2/13/2000 11:11:00 AM
From: Dan3	Read Replies (1) \| Respond to of 1574004

Re: 8 times as many addresses can fit into the same cache index.... Thanks for your correction of my post. I had understood the increase in set associativity allowed for more addresses to be maintained in a given set, not that there were more indexes available. e.g. a 2-way would have greater granularity but less depth. This led to my expectation that a 16-way would keep track of more addresses with the same least significant bits (that would be overwritten in the 2-way cache), while failing to maintain as many bytes of each sequential access. The net result would be that the 16-way and 2-way would, after repeated accesses to each set of low order addresses, be left with limited overlap of cached locations. I'm guess I'm still a bit confused, if a 128K 16-way and 2-way cache don't behave identically, why, after an extended period of repeated accesses to each region of memory, would they both be left with the same set of addressed in cache? (so that the there would be 100% duplication of the L1 in the L2) Thanks for your post, Dan