Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Saturn V who wrote (99010)	2/14/2000 6:42:00 PM
From: Process Boy	Read Replies (1) \| Respond to of 186894

Saturn - <Is Process Boy in a position to comment ?> Several things. * - I cannot verify the source of the info semi posted. However, by tomorrow I could probably obtain figures myself. However, I would not be able to relay this information directly. Let's see what happens tomorrow.... * - re: Glut? Going forward there may be several items either going into or maybe even already into production, e.g., Cascades, Willamette, Foster, Merced, Timna, which have relatively big die sizes compared to Cumine. Think about Timna production alone. I am not worried about supply gluts going forward at this point, and especially not at the moment with the stings of GTW and DELL fresh in my memory. PB

To: Saturn V who wrote (99010)	2/14/2000 6:44:00 PM
From: semiconeng	Read Replies (2) \| Respond to of 186894

Hi SemiConEng, Like Elmer, I am also a skeptic about the information you posted.If one fab produce 1 million finished coppermines/wk (ie 52 million coppermines/yr) there will be a massive glut within a few months. Could the poster be referencing all the 0.18micron fabs producing 1 million per week ? That is consistent with Intel management guidance of >10 million coppermines in Q1. Or could it be refering to good die on wafers, ie excluding losses in package, assembly burn-in and test and assembly. Even then it seems high since I would not expect losses in these operations to exceed 15 percent. Or are we talking about including the 0.18micron Celeron ? I do not expect 0.18micron Celeron introduction for a few more quarters. Is Process Boy in a position to comment ? Thanks Point taken. I know that F12 has Wafer Sort on-site, but there is no Assembly/Test. I'm sure that there will be losses during the "C4 Bump Assembly", and probably more losses at "Burn In", and more losses at "Final Test". I doubt that all of those 1,000,000 die will make it past those 3 steps in the process. All I'm saying is what I saw. The header on the poster said F12 Ocotillo shipped...... Since Elmer has stated that he lives in the area, and since there is a poster in the lobby that he can see, I invite him to do so. SemiConEng