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To: rudedog who wrote (99101)2/15/2000 6:17:00 AM
From: Joseph Pareti  Read Replies (1) | Respond to of 186894
 
I would appreciate if anyone could verify the following statements about IA-64.

assume the following code
t1 = LOAD a0
t2 = ADD t1,1
t3 = LOAD a1
t4 = ADD t3,1

an out-of-order processor will delay the ADD that is dependent on the load, but it will continue fetching and executing instructions that are not dependent on the LOAD.

The in-order machine (IA-64) will stall all the ADD instructions and will not execute any further instructions until the load completes, resulting in a x-cycle stall, where x depends whether there is a cache hit or miss.



To: rudedog who wrote (99101)2/15/2000 9:59:00 AM
From: Elmer  Read Replies (1) | Respond to of 186894
 
Re: "My point was simply that the EV6 bus was developed for Alpha 4-way machines and is obviously a very capable high performance SMP bus architecture - those are pretty fast machines. It is not any limitation of EV6 which is holding back AMD in the SMP space... "

I don't think it's a limitation of EV6 either. I think it's a bug in Athlon but AMD refuses to publish their errata list so we don't know for sure.

EP


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