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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Jeffrey D who wrote (34298)	2/17/2000 9:32:00 AM
From: Proud_Infidel	Respond to of 70976

Orders Accelerate for Applied Materials' Dielectric Etch Technology More Than 200 Dielectric Etch Super e Chambers Shipped, 50th Multi-Chamber System Installed at TSMC SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 17, 2000--Applied Materials, Inc., the world's leading supplier of etch equipment to the semiconductor industry, has shipped more than 200 Dielectric Etch Super e(TM) chambers. The latest of these chambers is installed on the company's 50th multi-chamber Dielectric Etch Super e Centura® system which was purchased by Taiwan Semiconductor Manufacturing Company (TSMC) for their newest high-volume foundry facility in Hsinchu, Taiwan. This 200th chamber, 50th system milestone was achieved less than six months after the system's introduction in July 1999 and includes repeat orders as well as upgrades and retrofits. Jiunn-Jyi Lin, director and chairman of TSMC's etch technical board, said, ''The Dielectric Etch Super e Centura's fast installation and high throughput has helped us quickly ramp production capacity in order to meet the rapidly growing demand for TSMC products. Multiple systems are now being used in production at TSMC's advanced fabs. The Super e system represents an impressive extension of etch technology; its rapid qualification, high productivity and impressive reliability have been key factors in achieving our manufacturing targets.'' TSMC is currently using the Dielectric Etch Super e system in volume production for 0.25 micron via and pad etch applications, as well as in the development of 0.18 micron etch applications. ''TSMC's assistance has been invaluable in qualifying the production capabilities of the Dielectric Etch Super e system. We have taken the Super e from initial testing at TSMC to broad acceptance in many of TSMC's fabs in under one year,'' noted Diana Ma, vice president and general manager of Applied Materials' dielectric etch product group. ''The Super e system's flexibility, reliability, and productivity are being demonstrated daily inside TSMC fabs.'' Applied Materials has an installed base of more than 1,500 MxP+ series dielectric etch process chambers, which can be upgraded with the new Super e chamber's advanced hardware features and performance. Super e chambers are also available on Applied Materials' newest etch platform, the Centura II, which offers additional benefits in ease of installation and serviceability. The Dielectric Etch Super e was designed with several key process and productivity advancements to meet the high volume requirements of leading-edge foundries. New features include high etch rates, reduced wafer handling time and a ceramic electrostatic chuck, making the system ideally suited for advanced via, contact, pad, spacer and hard mask open etch applications. According to Dataquest, a market research firm, a preliminary estimate of the market for dielectric etch equipment in 1999 was $1.02 billion. This market is projected to grow to $2.04 billion by the year 2004. Applied Materials, Inc. is a Fortune 500 global growth company and the world's largest supplier of wafer fabrication systems and services to the global semiconductor industry. Applied Materials is traded on the Nasdaq National Market System under the symbol ''AMAT.'' Applied Materials' web site is appliedmaterials.com.

To: Jeffrey D who wrote (34298)	2/17/2000 11:04:00 AM
From: Gottfried	Read Replies (1) \| Respond to of 70976

Jeffrey, OT *** OT Make sure you're not swallowing coffee while this page opens. :)http://home.att.net/~dynamogold/silicon/enquirer.html Gottfried Thanks, LK2.

To: Jeffrey D who wrote (34298)	2/17/2000 12:38:00 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 70976

"Red brick wall" probably won't faze chip makers, says TI's Doering By Bill McIlvaine Semiconductor Business News (02/17/00, 10:32:20 AM EDT) BURLINGTON, Mass. -- Fears of hitting a "red brick wall" in semiconductor technology in the next 10 to 15 years don't appear to be stopping semiconductor makers' headlong rush to meet it, said Robert Doering, senior fellow in silicon technology development at Texas Instruments Inc., addressing a SEMI New England breakfast forum here Wednesday. While it always remains possible the industry will find innovative ways to overcome those obstacles, he said, the industry has also always counted on pushing the wall a little further back. At this point it seems to remain implacable, at least for now. "The brick wall has held steady for the last few roadmaps," Doering said. "It's not a wall on wheels." When the Semiconductor Industry Association released the 1999 International Technology Roadmap for Semiconductors last fall, it included a list of technical hurdles -- called the "red brick wall" -- that it expected to hit in the next decade and a half. Some of those include pushing DRAM half-pitch below 180 nm by 2002, reducing MPU gate lengths to 65 nm by 2005, and developing inter-metal dielectrics with k constants as low as 1.6 by 2005. Most appear reachable, said Doering, although "there are questions about which solution will work" or if the time frame for finding solutions can stay on track. Then there is a red area where there is no consensus on solutions, he said, where the industry needs real breakthroughs. This has happened before, such as when the industry developed deep ultraviolet lithography, step-and-repeat on-wafer patterning, and the MOS transistor, Doering pointed out. Perhaps the most formidable brick-wall barrier is finding a successor dielectric interconnect material to the venerable silicon dioxide, which "is nearing the end of its life," said Doering. "If we are to continue to reach the new smaller gate lengths of future generation nodes, we must find a new dielectric material." Current silicon dioxide dieletric material must now be no more than four of five atoms thick in order to give the high performance needed in leading-edge chips. According to TI's Doering, the chip industry has about reached the physical limit of how thin silicon dioxide lines can be made. Doering believed that in the near term -- for the next three to four years -- silicon nitride can become a new dielectric for high performance chip interconnect. "In the longer term, of the next 5 to 10 years, even more revolutionary materials will be needed," he said. Two classes of new materials for the long term are under study: metal oxides and metal silicates. He listed titanium oxide as a promising dielectric. The metal silicates add oxygen to metals such as titanium or zirconium. He said some researchers are looking at ferroelectric materials for very dense interconnect lines. This includes some of the materials, such as BST (barium strontium titanate) that is also being considered by DRAM makers for very dense capacitors. The TI researcher said, "Chemistry is marvelous and they always come up with a way" to leap a technical hurdle. But he indicated that the average time it takes for a breakthrough technology or tool to go from development to production is six years. "So you have to start early," he said. According to the SIA roadmap, the red brick wall for dielectrics, junction depths and oxide replacements is positioned squarely at 2005. "The hope is that it will recede. There's not evidence of that yet," Doering said. He said it was likely that chip makers would simply rush to the limit. "They probably will push as fast as possible rather than maximizing the profit from each node," the TI researcher said. "Competition is fierce and people will try to get there as fast as they can." And the hoped-for breakthroughs may well materialize, given past experience he said. But then the question will be whether the new technologies could be too expensive to be cost effective.