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To: Tenchusatsu who wrote (99341)	2/17/2000 2:45:00 AM
From: Mihaela	Respond to of 186894

Excellent work/chipset Ten! ;) 870 will work both for Foster (IA-32 server version of Willamette) and McKinley (IA-64 follow-on to Merced/Itanium).

To: Tenchusatsu who wrote (99341)	2/17/2000 2:53:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Ten - Re: "The main feature of the 870 chipset is the Scalability Port. Here's what the article says regarding SP" The EE Times article described the 870 as a chip set that would link groups of 4-way SMP Fosters. Does this imply that the 4-way Fosters will have their own 4-way SMP chip set (Colusa ?)and that the 870 is a "Chip set for Chip Sets" ? Paul

To: Tenchusatsu who wrote (99341)	2/17/2000 5:49:00 AM
From: Steve Lee	Read Replies (1) \| Respond to of 186894

Re: "870 will work both for Foster (IA-32 server version of Willamette) and McKinley (IA-64 follow-on to Merced/Itanium). The chipset will also support both DDR SDRAM and RDRAM" Does this mean we will see Rambus in IA64 machines?

To: Tenchusatsu who wrote (99341)	2/17/2000 9:35:00 AM
From: Tony Viola	Read Replies (1) \| Respond to of 186894

Ten, >"With the new scalability port we can link two or more 4-way systems," Rattner said. "This allows OEMs to build 8-, 12- or 16-way systems." Definitely good stuff for high performance systems. Does this mean that the performance penalty multiplier up to, like 16 way, will be like that of a "pure" 16 way SMP system? Like with 8 ways, you "only" get something like 0.75X8 = 6 equivalent CPUs worth of processing power, which is still great compared with a clustering penalty. That's because of overhead. I appreciate having Intel engineers on this thread, giving us real world info about the products where they can, within NDA limits. The AMD thread, as technical as they like to be, don't have any AMD engineers, at least that have come forward. Advantage, Intel investor. Tony