To: Dan3 who wrote (93947 ) 2/17/2000 9:53:00 PM From: Tenchusatsu Read Replies (2) | Respond to of 1571699
Dan, <That's what AMD is using in the 760 chipset. But those extra pins and board traces may add as much as $15 or even $30 to the cost of the board / memory subsystem> As usual, Dan, you're tossing up assumptions in the air and passing them off as fact. I can guarantee you that the 760's north bridge alone will cost at least $60 more to manufacture than the Tehama north bridge. (That 760 north bridge will have well over 1,000 pins; 840's north bridge isn't even above 500, and Tehama will probably add another 100 pins because of the Willamette/Foster bus.) Then add electricals, board traces, etc., and you're looking at another $60 to $100. Gee, that turns out to be $120 to $160 of additional cost just for the motherboard. Better hope RDRAM prices stay sky-high forever. (Better hope DDR-266 yields pretty well, too; seems like the intro of a DDR-200 speed grade wouldn't be necessary if 266 were yielding well.) <for only 4.2 Gigabytes/Sec transfer rate - at least it will be a sustainable streaming rate (interleaved memory).> Wrong again, Dan. This will DEFINITELY not be a "sustainable streaming rate." Each channel can't even make efficient use of the 2.1 GB/sec bandwidth. What makes you think interleaving them is going to increase the per-channel efficiency all-of-a-sudden? <Meanwhile the 3.2 Gigabyte/Sec of Dual rambus comes at - no cost?> It's here already, no? When is AMD's 760 chipset being released? By the way, Intel expects Timna to move from SDRAM (via RDRAM-to-SDRAM translator) to native RDRAM later on (like 2001). Take a look:eet.com Asked why Intel didn't create a Timna with an SDRAM interface on the processor, MacWilliams said that such an approach would have required too many pins on the package and that the buffers and I/O transistors would bloat the die. Still think those extra pins on the 760 north bridge will come for mere pennies? Tenchusatsu