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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (95359)	2/27/2000 10:42:00 AM
From: steve harris	Respond to of 1578238

Thread, Tom's has an article today from CeBit show. Mostly pictures of the Thunderbird. www7.tomshardware.com steve

To: Dan3 who wrote (95359)	2/27/2000 12:42:00 PM
From: Scumbria	Respond to of 1578238

Dan, Is there anything about a longer pipeline that is problematic? Longer pipelines require a lot of thought at the beginning of the project. It is essential to divide the pipe up into evenly sized blocks. They also require more storage elements to preserve state between stages. Does the scheduler now need to (accurately, in order to maintain performance) predict branches further out? In any pipeline you want to predict branches as early as possible. This is done by looking up the current instruction fetch address in a branch target buffer. If a match is found, the next fetch is from the branch target address. There really isn't any such concept as a scheduler any more. High speed design does not allow for global control of the pipeline, because it would require complicated logic and long wires. Scumbria

To: Dan3 who wrote (95359)	2/27/2000 1:31:00 PM
From: Dan3	Read Replies (1) \| Respond to of 1578238

Probably already posted, but there is a fascinating discussion of chip architecture by Chris Rijk on Ace's Hardware at: aceshardware.com Although the article is centered upon decisions made in the design of the UltraSparc III, it includes extensive discussion of almost all aspects of CPU, cache, and bus design. Grab a cup of coffee and settle back for a long, enjoyable read. Comparisons are made to competing architectures as well (though few to either Athlon or Willamette). A great article. Dan