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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (95385)	2/27/2000 3:07:00 PM
From: Dan3	Read Replies (1) \| Respond to of 1578501

Re: The discussion of load latency was grossly inaccurate... Huh! Thanks for your quick review. Their linked-list example was fairly compelling, but only if they are correct about linked lists being common in compiled code. Did you really find the latency vs. pipline speed/length vs. ILP vs. branch handling discussion that far off? In all fairness, he did say he was basically translating Sun's published documentation for those (like me) who might have trouble following the originals. I'm encouraged that you are less than impressed by the US-3 since it, and Willamette, seem focused on long pipe, short latency L2 vs. Athlon with its shorter pipe, and longer latency L2, but better scheduling. Re: I'm rather surprised that they are bragging about a single-cycle cache, given that they missed their frequency target by about a factor of two... I think they went from 3 to 2, not 2 to 1 on the L1. I think the article did discuss the problems that occur when core design and simulation assume single cycle cache, then the actual silicon winds up at 2 or 3 cycles, rendering the scheduler design choices inappropriate. So, they are both running half the target speed and the L1 is still 2 cycles not 1. Regards, Dan