Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (96146)	3/1/2000 6:59:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1576586

Jozef, <Isn't this one area where Itanium may have an advantage, in that you pack several instructions into one 64 bit chunk of data?> In IA-64, three instructions are packed into one 128-bit chunk. Scumbria does have a valid concern regarding code bloat. Unlike CISC or even RISC, IA-64 instructions always come in packs of threes, and each instruction cannot depend on the results of the other two. That means if you have a piece of code that does not allow for instruction-level parallelism, that means only one instruction can be inserted into each 128-bit chunk. The resulting worst-case scenario would be an increase in code size by a factor of three. On the other hand, I have to wonder whether code bloat really does become an issue in the real-world. I guess that's yet another reason why the compiler has to be good, not only to increase the number of instructions executed per clock, but also to pack as many instructions as possible into a given amount of space. And certainly the issue of compilers has been a touchy one when it comes to Itanium's potential performance. Tenchusatsu

To: Joe NYC who wrote (96146)	3/1/2000 8:16:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1576586

Joe, Isn't this one area where Itanium may have an advantage, in that you pack several instructions into one 64 bit chunk of data? IA64 is still a load-store architecture, so the effective code density will not be as good as x86. This is because a separate instruction is required for a load and an execute, whereas x86 instructions can do both in a single instruction. I'm guessing that IA-64 code density is somewhat better than most RISC processors, but let's not forget that VLIW stands for "very long instruction word". Scumbria