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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (98784)	3/17/2000 1:06:00 PM
From: Hans de Vries	Read Replies (2) \| Respond to of 1571175

Willamette's 3 GHz ALU revealed (at least a try...) Scumbria, This would be the most optimized version of the Willamette's ALU: The ALU in Willamette's post Trace Cache pipeline =====#=======================#=======================#===== # Pipeline stage 17 # pipeline stage 18 # # # # # "E X E C U T E" # "F L A G S" # # # # # \| # \| # # ALU1 \| ALU2 # ALU3 \| FLAGS # =====#===========+===========#===========+===========#===== ^ \| \| \| \| \| \| \| +-----------+ \| \| logic functions \| \| ^ feedback \| \| \| \| \| +-----------------------+ \| fixed length shift functions \| ^ feedback \| \| \| +-----------------------------------+ add/subtract, variable shift functions feedback Functions like AND, OR, XOR take 0.5 clock cycle. Functions like A>>5, A<<3 take 1.0 clock cycle. Functions like A+B, A-B, A<<B take 1.5 clock cycle. The slowest function in the FLAGS section is the 8 bit parity flag to bit 2 of the EFLAGS register. The propagation delay for this function (two 3-input XOR's) is about 1/3 of the longest ALU path (32 bit adder/subtractor plus selectors). So the above pipeline is well balanced. Regards Hans. P.S. The Willamette uses dynamic logic but so does the Coppermine and earlier Pentium processors