Everyone probably already saw this. This Prism tech. should be out in 2001.
Sitera to develop network processor variants quickly
By Loring Wirbel
EE Times
(04/13/00, 11:34 a.m. EST)
LONGMONT, Colo. ? Sitera Inc. is relying on standardized use of the tool command language (TCL) and a method of using networked hardware development platforms in a "known-good-part" environment to quickly develop spins of the Prism network processor family it introduced this month.
The notion of employing standard scripts and multiple agents as target platforms arose from Sitera's use of its own NetPCI prototype development processor to optimize feature sets for the Prism family.
Chris Kerner, director of Prism programming at Sitera, said the ability to develop applications like routing subroutines quickly will let customers transfer the knowledge gained by the company's internal developers to customers' own application developments. Sitera's software development environment uses many of the same tools to let customers have full visibility into Prism subsystem blocks like the order manager, which prioritizes Internet Protocol packets. The Developer's Workbench environment is combined with a commercial library Sitera calls SoftNet, which provides both direct forwarding code for standard datapath tasks like routing, as well as a series of application programming interfaces to translate high-level calls to assembly-level routines.
Sitera is on schedule to receive three IQ2000 Prism family members from its foundry, United Microelectronics Corp., this spring: the S21132 with a 32-bit I/O for input and output; the S21102, offering 16- or 32-bit interfaces to the fabric and dual Gigabit Ethernet interfaces to the enterprise; and the S21100, which offers 16- or 32-bit interfaces to the fabric and a dual 16-bit interface scaled from OC-3 (155-Mbits/second) to OC-12 (622-Mbits/s) speeds, for aggregation over mid-range Sonet speeds.
The transition from enterprise switching to edge routing and switching close to the WAN has meant that Sitera has to offer more flexible programming environments than might have been necessary in a LAN world dominated by Gigabit Ethernet uplinks, said Sitera president Steve Flannery.
"There's no question, if you look at where we were 18 months ago, that the key focus was on higher performance core and edge switching within the enterprise," Flannery said. "But as we started working with key beta customers over the last few months, the interest evolved to intelligent edge applications, in systems used by service providers rather than enterprises."
Because the development environment was designed for flexibility from the beginning, few changes in core hardware were necessary as attention shifted away from the LAN, said chief technology officer Steve Sheafor. But Sitera developers had to consider a wider range of packet buffering and quality-of-service (QoS) parameters to deal with aggregated WAN traffic, as Prism evolved to take on more public networking duties.
No centralized RISC
A key difference in Sitera's Prism IQ2000 architecture is its lack of a centralized RISC host on the network processor chip. Instead, the core architecture relies on four highly optimized 200-MHz Stanford RISC-like processors called "Facet" cores, which serve as forwarding engines to the Prism Rambus interface. The Facet 32-bit core is combined with a 5-port register file, a lookup coprocessor and a DMA engine in each of the four forwarding blocks. Prism family members still require some form of host processor, such as a MIPS or PowerPC controller.
Sheafor offered three main reasons for not embedding the host controller on the primary network processor: it required a large and complex block that could make intrachip communications more difficult; it required code complexity in the range of 10,000 to 20,000 lines, vs. 4,000 for Prism; it required customers to meet such diverse demands in the control plane that it made sense to separate many functions from the forwarding engines.
Before incoming packets hit the four Facet CPUs, they are preprocessed by small classification engines that perform functions like TCP checksums on the packets. They then hit a key block within Prism called the order manager, which serves as an on-chip load balancer. Order manager assigns packets to one of the four CPUs based on traffic loads.
Packets assigned to a Facet core travel across the internal streaming bus, the Fusion bus, which also communicates to the host interface and the Rambus controller but is invisible to customers. Sheafor said the decision to rely on Rambus for primary memory control happened early in the Prism design cycle, since alternatives like synchronous or DDR DRAM would require too much parallelism in memory. In any event, the entire Prism architecture is oriented around the use of dynamic, rather than static, RAM.
The Facet blocks can handle multiple context threads. Since context management is handled in hardware, the multithreading appears to the application developer as a single logical entity processing packets. The Facet CPUs can achieve up to 95 percent utilization levels. Because of the high efficiency of the Facet forwarding engines and the high speed of the Rambus memory interface, no caching is implemented in the Prism system.
Traffic management
After packets have been processed in the Facet blocks, they are sent to a queue manager on the Prism chips, which allocates how packets are sent to general-purpose output queues. This manager cooperates closely with the internal QoS engines, the last stop in the Prism chip before a packet is sent out to the network. The QoS engines determine how reservation-based and flow-based QoS policies can be assigned. The Prism chips provide direct hardware support for common queuing algorithms such as round robin, weighted round robin and weighted fair queuing. The combination of queue manager and QoS engine can implement advanced congestion-management policies like random early discard and weighted random early discard.
In contrast to the internal streaming FusionBus, customers wanted an external I/O bus that allowed choices in implementation. Because the Utopia interface for asynchronous transfer mode was considered too slow, while the emerging Packet Over Sonet Physical standard did not exist, Sitera elected to implement its own FocusBus interface. It is bidirectional and could be implemented in increments like quad 3.2-Gbit/second channels or octal 1.6-Gbit/s channels.
Dave Dubois, director of product strategy at Sitera, said that the Rambus interface acts as an explicit segmentation between control plane and forwarding plane duties. Since most application developers are comfortable with writing applications in the control plane, Sitera structures its APIs to provide customers with control interfaces, limiting the development of forwarding code to a few thousand lines.
Wade Appelman, vice president of marketing, said that one of the company's best design disciplines is that of using similar programming tools for both internal acceleration in the development of Prism alternatives and external provision of workbench tools for customers. The hardware development platform Sitera delivers with its Developer's Workbench is functionally equivalent to a dual-port Gigabit Ethernet switch. Sitera thought it had to develop dedicated RFC 1812 router code for the hardware development system.
The "known-good-part" methodology allows software routines to be sent to multiple target hardware development systems. These systems often are located in different physical locations within Sitera's test lab, allowing true distributed testing of target systems.
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