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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Daniel Schuh who wrote (39928)	4/14/2000 9:53:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 93625

Dan, Why would I want to pay $85 for 128MB SDRAM when I can buy just as much RDRAM for only $600? Scumbria

To: Daniel Schuh who wrote (39928)	4/15/2000 2:14:00 AM
From: Bilow	Respond to of 93625

Hi Daniel Schuh; If you believe the dramreview.com website, which is very tightly connected to Rambus, they are probably not trying to patent double edge clocking (which undoubtedly dates to the 40s or 50s). Instead, they are claiming patents on the use of a register to adjust the CAS length of synchronized DRAM, and the use of a PLL, for instance. See the above website for the details, it is quite explicit, complete with patent links: dramreview.com dramreview.com My guess is that the above website's analysis is similar to the one that Rambus is using, but I haven't looked at any court papers. There are a lot of patent issues, I intend on looking at them one at a time. I will start with the adjustable CAS cycle time first. I'm pretty sure that the PLL issue is dead. A lot of chips use PLLs to adjust timing between chips, and this is what is basically going on. DDR SDRAM are not chained like RDRAM is, so the patent will have to be general enough to cover a good bit of chips that use a PLL (or DLL) to adjust internal clocking. Rambus is also not claiming a patent on the concept of adding registers to a memory chip and making it synchronous. They can't because, as I mentioned on this thread before, synchronous memory long predates Rambus in the SRAM market. In fact, that whole idea probably falls in the "skilled in the art" class. All it really boils down to is the integration of external parts into the memory chip. My feeling is that the stuff that Rambus is claiming with respect to SDRAM and DDR patents having to do with the synchronous stuff is probably stuff that is a direct consequence of the addition of the synchronizing I/O flip-flops. For example, memory has long had programmable internal registers. Before SDRAM, those registers were addressed by applying unique patterns to the RAS, CAS, and other control lines (like TROE, if I remember correctly). Adding synchronizing registers causes that method to be transferred to a technique that is quite similar to the way that SDRAM's (and DDR's) internal registers are addressed. But it will be a long time before I comment further on this, I have a lot of long research to do. -- Carl