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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Dave B who wrote (40162)	4/17/2000 10:51:00 PM
From: Ali Chen	Read Replies (1) \| Respond to of 93625

Dave, <Rambus has announced that this Summer they'll demo RDRAM at 4x the current throughput (6.4MBs) by doubling the width and doubling the speed.> Three remarks are in order: 1) It is possible to demo anything. They demoed the Ram-bus in 199-when? So what? The real challenge is to produce "en Masse" and within competitive cost. 2) "by doubling the width" - finally they see the light at the end of their tunnel... 3) "and doubling the speed" This must be the best joke I ever heard! <When do you think DDR will get there?> Definitely never. Nothing can compete with the hype of this scale! Respectfully, - Ali Chen.

To: Dave B who wrote (40162)	4/18/2000 1:03:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 93625

Dave, I'm not sure what value increasing the DRAM bandwidth provides a CPU. Assume a 1.0 GHz CPU accesses DRAM 1% of the time (1% is very high for cache misses in the L1+L2.) Each cache miss brings in 32 bytes. The bandwidth requirement is: 1,000,000,000 cycles/sec X .01 dram accesses/cycle X 32 bytes/dram access = 320MB/S. As evidenced by the Intel charts, cheap SDRAM provides plenty of bandwidth to meet this requirement. The actual bandwidth requirements are considerably less because I am assuming that most L2 accesses are missing. Also evident from the Intel chart is the fact that SDRAM provides better latency until the it gets saturated, which should not occur very often. Scumbria

To: Dave B who wrote (40162)	4/18/2000 7:59:00 AM
From: gnuman	Read Replies (1) \| Respond to of 93625

Dave B. re<Rambus has announced that this Summer they'll demo RDRAM at 4x the current throughput (6.4MBs) by doubling the width and doubling the speed.> Any insight into the packaging? Currently the mother boards and RIMM's appear use 66 pins for data. (16RSL in/out, 17 grnd in/out. (Non ECC). From Intel's 820 chip set design guide: ftp://download.intel.com/design/chipsets/designex/29063103.pdf (A big .pdf file, but an interesting read). Intel states there should be a 10 mil ground trace bracketing each RSL trace to minimize cross coupling of signals. (Page 2-10). In fact the reason a RIMM seems to require a 184 pin connector is the liberal use of grounds to control impedance, minimize cross talk and prevent image current spreading. If they double the width of the data channel, wouldn't that add 66 pins to the package? JMHO's TIA