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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Don Green who wrote (40539)	4/21/2000 6:52:00 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi Don Green; Re the patent disputes... I think it is just barely beginning to become clear to all concerned that DDR and SDRAM really do pose a threat to RDRAM. Rambus' ace in the hole is the patents it has, and how they apply to SDRAM. I would now like to begin talking about those patents. Just a few steps in the general direction, nothing serious. First, it is sort of amazing how many patents are around that have something to do with SDRAM. I never managed to stumble upon a Rambus patent, I am sure that if I searched harder I could find one, though. But what amazed me was just how many patents there are on DRAM out there. Given that Rambus' original intent was to protect RDRAM, rather than to cover SDRAM, you would think it unlikely that they are in possession of a significant percentage of the IP related to SDRAM. As an example, the original patent on synchronous memory is fairly old, and belongs to IBM. 1987/1985 IBM High performance memory system utilizing pipelining techniques A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer. Consequently, as a result of the use of these latch circuits in a memory system, pipelining techniques are utilized in the memory system for the improvement of the performance of the memory system. patents.ibm.com Burst access mode was patented by TI: 1985/1982 Texas Instruments A semiconductor memory device contains an on-chip self-incrementing counter which may be loaded from address input terminals, so that the memory cell array may be accessed using either an incoming address or the last address incremented by one. patents.ibm.com The crucial (my opinion) patent that covers a single synchronous memory device having either 2 or 3 cycles of pipeline delay (i.e. CAS-2 or CAS-3) is owned by Hitachi, but isn't terribly easy to understand by those not familiar with how these things work, it will probably not be obvious to mom and pop that this what the following is talking about. (Or maybe it is too late at night for me to tell as well.) 1994/1993 Hitachi DRAM having addressing and/or data transferring path arranged in pipeline architecture. patents.ibm.com As an example, Rambus is claiming a patent not on the idea of having an SDRAM that is either 2 or 3 CAS cycles in access, but instead on the idea of how the control bit that selects between these modes is input into the chip. The above patent doesn't specify how the bit is input. I think that the details of how the bit is set falls under prior art, in particular the techniques for setting control bits in VRAM. But I am really just posting these links here so that I can find them later. I've got a lot of stuff to digest, and will take a look at the dramreview.com patent stuff probably this weekend. The use of PLLs and DLLs for arranging to have data stable at the time of the incoming clock edge (or changing coincident with the incoming clock edge), is ancient and patented in numerous versions. My personal favorites would be: 1982/1980 Delay Locked Loop, Control Data Corp. patents.ibm.com Issued 1985, DLL Micro Component Technology, Inc. patents.ibm.com Of course any EE would naturally use a DLL to minimize skew, so it might not be patented as such, being obvious, but there are also a lot of patents having to do with particular ways of doing this. 1992/1991 DELAY LOCK LOOP CIRCUIT FOR CLOCK SYNCHRONISM patents.ibm.com 1990/1988 Clock distribution circuit having minimal skew, Motorola patents.ibm.com You have to wonder how much art is described in various old publications, particularly those having to do with DRAM: 1998/1995 Samsung Data receiving method and circuit for digital communication system 500Mbyte/sec Data-Rate 512Kx9 DRAM Using a Novel I/O Interface, N. Kushiyama et al. 1992 Symposium on VLSI Circuits digest of Technical Papers, pp 66-67. patents.ibm.com Some more patents of interest: 1993/1990 Extended frequency range variable delay locked loop for clock synchronization, Xerox patents.ibm.com Issued 1995, Motorola Inc., SDRAM type: patents.ibm.com -- Carl