SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (107314)4/22/2000 12:28:00 AM
From: Joe NYC  Read Replies (2) | Respond to of 1572918
 
Scumbria,

I'm glad to see a lot of articles appearing in the press explaining that memory latency is far more important than bandwidth for desktop performance.

2 questions:

1. Do you find the cache hit rates they use in the ballpark? They have a hit rate of 128K L1 at 95%, additional 512K L2 at 80%, 256K at 78%, 64K at 65%. What would be the hit rate of 32K L1 (Pentium), or let's say going from 256K L2 to 512K, 1MB, 2MB. Is there an easy to remember formula to get the hit rates?

2. There was some talk on RMBS thread about the amount of time it takes to fill a cache line. How many bytes are in a cache line on Piii, Athlon? Does the CPU have to wait until the cache line is full, or can it start to use the data as it comes?

Joe