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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Pravin Kamdar who wrote (107718)	4/25/2000 3:41:00 AM
From: Joe NYC	Read Replies (1) \| Respond to of 1572777

Tom's review of Cyrix III: www6.tomshardware.com This chip really sucks. It may be even worse than Cyrix MII if it ran at 400 MHz. The road map looks poor too: Doug told us that Via is planning to shrink the Cyrix III from the current 0.18 micron process to a 0.15 micron process in order to introduce PR566 and PR600 chips in Q1, 2001. ...The Samuel, designed by the IDT team, will arrive in late Q2 to early Q3 and should be available from 500 to 600 MHz this year. "Ezra" is the next generation processor after Samuel and should arrive in the first half of 2001. Ezra is being developed jointly by the Cyrix and IDT teams. Doug mentioned that both SSE and 3DNow! are being considered for the Ezra as well as both Socket 370 and Socket A, the socket architecture used by AMD's Spitfire. Joe

To: Pravin Kamdar who wrote (107718)	4/25/2000 9:19:00 AM
From: niceguy767	Read Replies (1) \| Respond to of 1572777

Pravin: Re: "Sold out, Great Dresden news, Great DDR news (760 must be sampling).... Somebody pinch me. Will the great news never end?!!!" Comment: Sounds like "lift-off" to me!

To: Pravin Kamdar who wrote (107718)	4/25/2000 10:11:00 AM
From: FJB	Read Replies (1) \| Respond to of 1572777

EDA breakthroughs needed for future chip designs ... The power density problem is so bad that if current trends continue, future chips could reach 2,000 W/cm2, about as "hot" as a nuclear reactor, Borkar warned. This is due not only to an increase in active power, but also leakage power, which will make the situation worse. One possible solution, he said, is to place more memory on-chip. Memory is more power-efficient than logic. Thus, Borkar said, "large integrated caches make more sense than larger units of logic." But in general, Borkar said, designers will have to trade off some performance to reduce power. This might mean using static logic instead of the higher performance, but more power-hungry, domino logic. It means developing techniques for leakage control, like employing "sleep transistors," which Borkar said can provide a thousand-fold savings in leakage power. But this technique is very hard to implement, he said, and it cries out for automated CAD tools. ... techweb.com