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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (108575)	4/30/2000 1:56:00 AM
From: minnow68	Read Replies (3) \| Respond to of 1571175

Joe, About Willy's bus width, it was my understanding that Willy has a dual channel RAMBUS controller built in. It was also my understanding that a RAMBUS channel is 16 bits wide. Therefore, I've been going on the assumption, for quite a while, that Willy has a 32-bit data path. I'm surprised that everyone seems to be surprised by this. Mike

To: Joe NYC who wrote (108575)	4/30/2000 12:36:00 PM
From: Dan3	Read Replies (1) \| Respond to of 1571175

Re: Willamette, according to the article, has a 32-bit bus.... I've not seen a clear description of that bus. My WAG from what I've seen is that there is no such thing as a "quad pumped 100MHZ 32 bit bus". I doubt anything but an analog device can get more than 2 bits from a cycle. What could exist is a 64 bit 200MHZ double pumped bus (which is what AMD has been shipping for nearly a year and is about to surpass) that is muxed to a 400MHZ data rate configuration 32 bits wide. The Intel / Rambus teams appear to be afraid to let anyone understand enough about their proposed products to make an informed decision regarding the worth of those products. Maybe they do have something really great and they're just trying to mislead AMD - but, with the exception of the coppermine cache, they've been hyping junk, not sandbagging, for the last year. OTOH, here is a quote that contradicts my WAG: ebnews.com According to Glenn Hinton, a fellow in Intel's High-Performance Microprocessor Division, the Willamette bus transfers data at the equivalent of 400 MHz: four bits of data are passed each cycle along a 100-MHz bus. As with rival Advanced Micro Devices Inc.'s EV-6 bus licensed from Digital Equipment Corp., the data rate can be increased in future chipsets. Intel said its method will be to either increase the frequency or the amount of data per clock. Regards, Dan

To: Joe NYC who wrote (108575)	4/30/2000 1:39:00 PM
From: milo_morai	Read Replies (1) \| Respond to of 1571175

I saw that.. I was looking at this info..T-Birds L2 Cache- 16-way... happy-cat.ne.jp -------------------------------------------------------------------------------- 00/04/28, 1:50pm - Whoa! Lookie-here ... the folks at Happy Cat have revealed some mildly shocking info about the Thunderbird. What's so bigwig here? The L2 cache is 16-way set associative, a level of associativity that frankly I believe has never been seen in x86 memory caches (please, correct me if I'm wrong). On top of this, if the L1 and L2 caches are exclusive to each other (as is the case on the Spitfire/Duron), the set associativity would increase to 18-way (16 for L2 plus 2 for L1). Um, at least, that's what I think the case is. I only recently pieced together what associativity is, so I'm tentative with anything that I say about it. ;) The net effect here would be to decrease the cache miss rate. This is basically the same result that you'd get from increasing the size of the cache. Because of the increase in associativity, this 256KB L2 cache may very well be equivalent to or better than a 2-way (or 4-way, maybe?) 512KB on-die nonexclusive L2 cache (eg, in miss rate and such). I'd quote Hennessy/Patterson (sp?), but I don't think that Quantitative listed cache sizes above 128KB in that funky little miss rate table. Now, I'm a much bigger fan of increasing cache size as opposed to increasing associativiy as a means of decreasing miss rates. I find it monumentally silly when people tout the "amazing" benefits of going from 2-way to 4-way. But I might be able to cheer on a move from 2-way to 18-way. We'll see, I guess. jc-news.com Milo